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DWC3 as implemented in Cavium SoC is using UCTL bridge unit between I/O interconnect and USB controller. Currently there is no bond with dwc3 core code, so if anything goes wrong in UCTL setup dwc3 is left in reset, which leads to bus error while trying to read any device register. Thus any failure in UCTL initialization ends with kernel panic. To avoid this move Octeon DWC3 glue code from arch/mips and make it proper glue driver which is used instead of dwc3-of-simple. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> Link: https://lore.kernel.org/r/ZMd/ReyiY7wS6DvN@lenoch Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
21 lines
577 B
Makefile
21 lines
577 B
Makefile
#
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# Makefile for the Cavium Octeon specific kernel interface routines
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# under Linux.
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#
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# This file is subject to the terms and conditions of the GNU General Public
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# License. See the file "COPYING" in the main directory of this archive
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# for more details.
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#
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# Copyright (C) 2005-2009 Cavium Networks
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#
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obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
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obj-y += dma-octeon.o
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obj-y += octeon-memcpy.o
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obj-y += executive/
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obj-y += crypto/
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obj-$(CONFIG_MTD) += flash_setup.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
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