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5b74c67660
struct clockdomain contains a struct powerdomain *pwrdm and const char *pwrdm_name. The pwrdm_name is only used at initialization to look up the appropriate pwrdm pointer. Combining these into a union saves about 100 bytes on 3430SDP. This patch should not cause any change in kernel function. Updated to gracefully handle autodeps that contain invalid powerdomains, per Russell King's review comments. Boot-tested on BeagleBoard ES2.1. linux-omap source commit is 718fc6cd4db902aa2242a736cc3feb8744a4c71a. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
308 lines
7.4 KiB
C
308 lines
7.4 KiB
C
/*
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* OMAP2/3 clockdomains
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*
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* Copyright (C) 2008 Texas Instruments, Inc.
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* Copyright (C) 2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
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#include <mach/clockdomain.h>
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/*
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* OMAP2/3-common clockdomains
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*/
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/* This is an implicit clockdomain - it is never defined as such in TRM */
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static struct clockdomain wkup_clkdm = {
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.name = "wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
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};
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/*
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* 2420-only clockdomains
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*/
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#if defined(CONFIG_ARCH_OMAP2420)
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static struct clockdomain mpu_2420_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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static struct clockdomain iva1_2420_clkdm = {
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.name = "iva1_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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#endif /* CONFIG_ARCH_OMAP2420 */
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/*
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* 2430-only clockdomains
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*/
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#if defined(CONFIG_ARCH_OMAP2430)
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static struct clockdomain mpu_2430_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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static struct clockdomain mdm_clkdm = {
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.name = "mdm_clkdm",
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.pwrdm = { .name = "mdm_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
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};
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#endif /* CONFIG_ARCH_OMAP2430 */
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/*
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* 24XX-only clockdomains
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*/
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#if defined(CONFIG_ARCH_OMAP24XX)
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static struct clockdomain dsp_clkdm = {
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.name = "dsp_clkdm",
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.pwrdm = { .name = "dsp_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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};
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static struct clockdomain gfx_24xx_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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};
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static struct clockdomain core_l3_24xx_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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};
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static struct clockdomain core_l4_24xx_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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};
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static struct clockdomain dss_24xx_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
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};
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#endif /* CONFIG_ARCH_OMAP24XX */
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/*
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* 34xx clockdomains
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*/
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#if defined(CONFIG_ARCH_OMAP34XX)
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static struct clockdomain mpu_34xx_clkdm = {
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.name = "mpu_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain neon_clkdm = {
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.name = "neon_clkdm",
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.pwrdm = { .name = "neon_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain iva2_clkdm = {
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.name = "iva2_clkdm",
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.pwrdm = { .name = "iva2_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain gfx_3430es1_clkdm = {
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.name = "gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
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};
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static struct clockdomain sgx_clkdm = {
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.name = "sgx_clkdm",
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.pwrdm = { .name = "sgx_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
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};
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/*
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* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
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* then that information was removed from the 34xx ES2+ TRM. It is
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* unclear whether the core is still there, but the clockdomain logic
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* is there, and must be programmed to an appropriate state if the
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* CORE clockdomain is to become inactive.
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*/
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static struct clockdomain d2d_clkdm = {
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.name = "d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain core_l3_34xx_clkdm = {
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.name = "core_l3_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain core_l4_34xx_clkdm = {
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.name = "core_l4_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.flags = CLKDM_CAN_HWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain dss_34xx_clkdm = {
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.name = "dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain cam_clkdm = {
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.name = "cam_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain usbhost_clkdm = {
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.name = "usbhost_clkdm",
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.pwrdm = { .name = "usbhost_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
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};
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static struct clockdomain per_clkdm = {
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.name = "per_clkdm",
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.pwrdm = { .name = "per_pwrdm" },
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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static struct clockdomain emu_clkdm = {
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.name = "emu_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
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.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
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};
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#endif /* CONFIG_ARCH_OMAP34XX */
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/*
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* Clockdomain-powerdomain hwsup dependencies (34XX only)
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*/
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static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
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{
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.pwrdm = { .name = "mpu_pwrdm" },
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm = { .name = "iva2_pwrdm" },
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
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},
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{
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.pwrdm = { .name = NULL },
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}
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};
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/*
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*
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*/
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static struct clockdomain *clockdomains_omap[] = {
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&wkup_clkdm,
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#ifdef CONFIG_ARCH_OMAP2420
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&mpu_2420_clkdm,
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&iva1_2420_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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&mpu_2430_clkdm,
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&mdm_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP24XX
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&dsp_clkdm,
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&gfx_24xx_clkdm,
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&core_l3_24xx_clkdm,
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&core_l4_24xx_clkdm,
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&dss_24xx_clkdm,
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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&mpu_34xx_clkdm,
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&neon_clkdm,
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&iva2_clkdm,
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&gfx_3430es1_clkdm,
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&sgx_clkdm,
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&d2d_clkdm,
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&core_l3_34xx_clkdm,
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&core_l4_34xx_clkdm,
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&dss_34xx_clkdm,
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&cam_clkdm,
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&usbhost_clkdm,
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&per_clkdm,
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&emu_clkdm,
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#endif
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NULL,
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};
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#endif
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