linux/drivers/clk/mediatek/clk-mt2712-vdec.c
weiyi.lu@mediatek.com e2f744a82d clk: mediatek: Add MT2712 clock support
Add MT2712 clock support, include topckgen, apmixedsys,
infracfg, pericfg, mcucfg and subsystem clocks.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
[sboyd@codeaurora.org: Static on top_clk_data]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-02 01:02:53 -07:00

95 lines
2.4 KiB
C

/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-mtk.h"
#include "clk-gate.h"
#include <dt-bindings/clock/mt2712-clk.h>
static const struct mtk_gate_regs vdec0_cg_regs = {
.set_ofs = 0x0,
.clr_ofs = 0x4,
.sta_ofs = 0x0,
};
static const struct mtk_gate_regs vdec1_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0xc,
.sta_ofs = 0x8,
};
#define GATE_VDEC0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vdec0_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr_inv, \
}
#define GATE_VDEC1(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.regs = &vdec1_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_setclr_inv, \
}
static const struct mtk_gate vdec_clks[] = {
/* VDEC0 */
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
/* VDEC1 */
GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
};
static int clk_mt2712_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
return r;
}
static const struct of_device_id of_match_clk_mt2712_vdec[] = {
{ .compatible = "mediatek,mt2712-vdecsys", },
{}
};
static struct platform_driver clk_mt2712_vdec_drv = {
.probe = clk_mt2712_vdec_probe,
.driver = {
.name = "clk-mt2712-vdec",
.of_match_table = of_match_clk_mt2712_vdec,
},
};
builtin_platform_driver(clk_mt2712_vdec_drv);