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Even on x86-64, I've found the need to break up a readq() into 2 readl() calls. According to the Intel datasheet for the E3-1200 processor: " Software must not access B0/D0/F0 32-bit memory-mapped registers with requests that cross a DW boundary. " (http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html p. 16) I can confirm this is true via several hard machine lockups. Thus, add explicit hi_lo_[readq|write]_q and lo_hi_[read|write]_q so that these uses are spelled out. Signed-off-by: Jason Baron <jbaron@akamai.com> Link: http://lkml.kernel.org/r/281f09da7ad01e5cea99737ec34d2399bdbbbf63.1403818526.git.jbaron@akamai.com Signed-off-by: Borislav Petkov <bp@suse.de>
32 lines
604 B
C
32 lines
604 B
C
#ifndef _ASM_IO_64_NONATOMIC_HI_LO_H_
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#define _ASM_IO_64_NONATOMIC_HI_LO_H_
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#include <linux/io.h>
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#include <asm-generic/int-ll64.h>
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static inline __u64 hi_lo_readq(const volatile void __iomem *addr)
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{
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const volatile u32 __iomem *p = addr;
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u32 low, high;
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high = readl(p + 1);
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low = readl(p);
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return low + ((u64)high << 32);
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}
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static inline void hi_lo_writeq(__u64 val, volatile void __iomem *addr)
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{
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writel(val >> 32, addr + 4);
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writel(val, addr);
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}
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#ifndef readq
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#define readq hi_lo_readq
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#endif
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#ifndef writeq
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#define writeq hi_lo_writeq
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#endif
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#endif /* _ASM_IO_64_NONATOMIC_HI_LO_H_ */
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