linux/arch/arm/boot/dts/armada-370-xp.dtsi
Thomas Petazzoni 46febc6366 ARM: mvebu: change the default PCIe apertures for Armada 370/XP
The latest Marvell bootloaders for various boards change the MBus
Window base address from 0xC0000000 to 0xF0000000, in order to make
more RAM in the first 4 GB actually usable by the kernel (RAM that is
covered by the MBus window is "shadowed" and therefore not usable).

However, our default PCIe memory and I/O apertures where sitting at
0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be
outside of the MBus Window range on those platforms. To make things
work, we have to ensure those apertures use addresses in the
0xF0000000 -> 0xFFFFFFFF range.

Of course this change of the MBus Window base address from 0xC0000000
to 0xF0000000 also comes with a change of the internal register base
address from 0xD0000000 to 0xF1000000.

We have therefore designed the following memory map:

 * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP
   GP and Armada XP DB.

 * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers.

 * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory.

 * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O.

 * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping

There is one exception to this layout: the Armada XP OpenBlocks, which
has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This
does not conflict with the current change for the PCIe I/O and memory
apertures, and continues to work because on Armada XP OpenBlocks, the
bootloader is an old one, and continues to have internal registers
mapped at 0xD0000000.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-06 19:59:37 +00:00

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/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
* Copyright (C) 2012 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
aliases {
eth0 = &eth0;
eth1 = &eth1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "marvell,sheeva-v7";
device_type = "cpu";
reg = <0>;
};
};
soc {
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&mpic>;
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <1>;
status = "disabled";
};
serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <1>;
status = "disabled";
};
coredivclk: corediv-clock@18740 {
compatible = "marvell,armada-370-corediv-clock";
reg = <0x18740 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
};
coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
status = "disabled";
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts = <8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
};
eth1: ethernet@74000 {
compatible = "marvell,armada-370-neta";
reg = <0x74000 0x4000>;
interrupts = <10>;
clocks = <&gateclk 3>;
status = "disabled";
};
sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
status = "disabled";
};
nand@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <113>;
clocks = <&coredivclk 0>;
status = "disabled";
};
mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
cap-mmc-highspeed;
status = "disabled";
};
};
};
clocks {
/* 2 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
};
};
};