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4543eda521
Need to swap the data fetched over i2c properly. This is the same fix as the endian fix for aux channel transactions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
142 lines
4 KiB
C
142 lines
4 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "atom.h"
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extern void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
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#define TARGET_HW_I2C_CLOCK 50
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/* these are a limitation of ProcessI2cChannelTransaction not the hw */
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#define ATOM_MAX_HW_I2C_WRITE 2
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#define ATOM_MAX_HW_I2C_READ 255
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static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
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u8 slave_addr, u8 flags,
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u8 *buf, u8 num)
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{
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struct drm_device *dev = chan->dev;
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struct radeon_device *rdev = dev->dev_private;
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PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
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unsigned char *base;
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u16 out;
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memset(&args, 0, sizeof(args));
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base = (unsigned char *)rdev->mode_info.atom_context->scratch;
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if (flags & HW_I2C_WRITE) {
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if (num > ATOM_MAX_HW_I2C_WRITE) {
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DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 2)\n", num);
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return -EINVAL;
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}
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memcpy(&out, buf, num);
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args.lpI2CDataOut = cpu_to_le16(out);
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} else {
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if (num > ATOM_MAX_HW_I2C_READ) {
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DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
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return -EINVAL;
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}
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}
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args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
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args.ucRegIndex = 0;
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args.ucTransBytes = num;
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args.ucSlaveAddr = slave_addr << 1;
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args.ucLineNumber = chan->rec.i2c_id;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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/* error */
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if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
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DRM_DEBUG_KMS("hw_i2c error\n");
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return -EIO;
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}
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if (!(flags & HW_I2C_WRITE))
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radeon_atom_copy_swap(buf, base, num, false);
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return 0;
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}
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int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
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struct i2c_msg *msgs, int num)
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{
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struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
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struct i2c_msg *p;
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int i, remaining, current_count, buffer_offset, max_bytes, ret;
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u8 buf = 0, flags;
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/* check for bus probe */
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p = &msgs[0];
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if ((num == 1) && (p->len == 0)) {
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ret = radeon_process_i2c_ch(i2c,
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p->addr, HW_I2C_WRITE,
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&buf, 1);
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if (ret)
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return ret;
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else
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return num;
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}
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for (i = 0; i < num; i++) {
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p = &msgs[i];
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remaining = p->len;
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buffer_offset = 0;
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/* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
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if (p->flags & I2C_M_RD) {
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max_bytes = ATOM_MAX_HW_I2C_READ;
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flags = HW_I2C_READ;
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} else {
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max_bytes = ATOM_MAX_HW_I2C_WRITE;
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flags = HW_I2C_WRITE;
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}
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while (remaining) {
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if (remaining > max_bytes)
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current_count = max_bytes;
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else
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current_count = remaining;
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ret = radeon_process_i2c_ch(i2c,
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p->addr, flags,
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&p->buf[buffer_offset], current_count);
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if (ret)
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return ret;
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remaining -= current_count;
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buffer_offset += current_count;
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}
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}
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return num;
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}
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u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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