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On POWER9, we no longer have the restriction that we had on POWER8 where all threads in a core have to be in the same partition, so the CPU threads are now independent. However, we still want to be able to run guests with a virtual SMT topology, if only to allow migration of guests from POWER8 systems to POWER9. A guest that has a virtual SMT mode greater than 1 will expect to be able to use the doorbell facility; it will expect the msgsndp and msgclrp instructions to work appropriately and to be able to read sensible values from the TIR (thread identification register) and DPDES (directed privileged doorbell exception status) special-purpose registers. However, since each CPU thread is a separate sub-processor in POWER9, these instructions and registers can only be used within a single CPU thread. In order for these instructions to appear to act correctly according to the guest's virtual SMT mode, we have to trap and emulate them. We cause them to trap by clearing the HFSCR_MSGP bit in the HFSCR register. The emulation is triggered by the hypervisor facility unavailable interrupt that occurs when the guest uses them. To cause a doorbell interrupt to occur within the guest, we set the DPDES register to 1. If the guest has interrupts enabled, the CPU will generate a doorbell interrupt and clear the DPDES register in hardware. The DPDES hardware register for the guest is saved in the vcpu->arch.vcore->dpdes field. Since this gets written by the guest exit code, other VCPUs wishing to cause a doorbell interrupt don't write that field directly, but instead set a vcpu->arch.doorbell_request flag. This is consumed and set to 0 by the guest entry code, which then sets DPDES to 1. Emulating reads of the DPDES register is somewhat involved, because it requires reading the doorbell pending interrupt status of all of the VCPU threads in the virtual core, and if any of those VCPUs are running, their doorbell status is only up-to-date in the hardware DPDES registers of the CPUs where they are running. In order to get a reasonable approximation of the current doorbell status, we send those CPUs an IPI, causing an exit from the guest which will update the vcpu->arch.vcore->dpdes field. We then use that value in constructing the emulated DPDES register value. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> |
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| .. | ||
| book3s.c | ||
| book3s.h | ||
| book3s_32_mmu.c | ||
| book3s_32_mmu_host.c | ||
| book3s_32_sr.S | ||
| book3s_64_mmu.c | ||
| book3s_64_mmu_host.c | ||
| book3s_64_mmu_hv.c | ||
| book3s_64_mmu_radix.c | ||
| book3s_64_slb.S | ||
| book3s_64_vio.c | ||
| book3s_64_vio_hv.c | ||
| book3s_emulate.c | ||
| book3s_exports.c | ||
| book3s_hv.c | ||
| book3s_hv_builtin.c | ||
| book3s_hv_hmi.c | ||
| book3s_hv_interrupts.S | ||
| book3s_hv_ras.c | ||
| book3s_hv_rm_mmu.c | ||
| book3s_hv_rm_xics.c | ||
| book3s_hv_rm_xive.c | ||
| book3s_hv_rmhandlers.S | ||
| book3s_interrupts.S | ||
| book3s_mmu_hpte.c | ||
| book3s_paired_singles.c | ||
| book3s_pr.c | ||
| book3s_pr_papr.c | ||
| book3s_rmhandlers.S | ||
| book3s_rtas.c | ||
| book3s_segment.S | ||
| book3s_xics.c | ||
| book3s_xics.h | ||
| book3s_xive.c | ||
| book3s_xive.h | ||
| book3s_xive_template.c | ||
| booke.c | ||
| booke.h | ||
| booke_emulate.c | ||
| booke_interrupts.S | ||
| bookehv_interrupts.S | ||
| e500.c | ||
| e500.h | ||
| e500_emulate.c | ||
| e500_mmu.c | ||
| e500_mmu_host.c | ||
| e500_mmu_host.h | ||
| e500mc.c | ||
| emulate.c | ||
| emulate_loadstore.c | ||
| fpu.S | ||
| irq.h | ||
| Kconfig | ||
| Makefile | ||
| mpic.c | ||
| powerpc.c | ||
| timing.c | ||
| timing.h | ||
| trace.h | ||
| trace_book3s.h | ||
| trace_booke.h | ||
| trace_hv.h | ||
| trace_pr.h | ||