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https://github.com/torvalds/linux
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8554004a02
Omitting suffixes from instructions in AT&T mode is bad practice when operand size cannot be determined by the assembler from register operands, and is likely going to be warned about by upstream GAS in the future (mine does already). Add the single missing suffix here. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/5A8AF5F602000078001A9230@prv-mh.provo.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
178 lines
4.4 KiB
ArmAsm
178 lines
4.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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*
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* Trampoline.S Derived from Setup.S by Linus Torvalds
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*
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* 4 Jan 1997 Michael Chastain: changed to gnu as.
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* 15 Sept 2005 Eric Biederman: 64bit PIC support
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*
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* Entry: CS:IP point to the start of our code, we are
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* in real mode with no stack, but the rest of the
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* trampoline page to make our stack and everything else
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* is a mystery.
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*
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* On entry to trampoline_start, the processor is in real mode
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* with 16-bit addressing and 16-bit data. CS has some value
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* and IP is zero. Thus, data addresses need to be absolute
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* (no relocation) and are taken with regard to r_base.
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*
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* With the addition of trampoline_level4_pgt this code can
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* now enter a 64bit kernel that lives at arbitrary 64bit
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* physical addresses.
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*
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* If you work on this file, check the object module with objdump
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* --full-contents --reloc to make sure there are no relocation
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* entries.
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*/
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#include <linux/linkage.h>
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#include <asm/pgtable_types.h>
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#include <asm/page_types.h>
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#include <asm/msr.h>
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#include <asm/segment.h>
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#include <asm/processor-flags.h>
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#include <asm/realmode.h>
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#include "realmode.h"
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.text
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.code16
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.balign PAGE_SIZE
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ENTRY(trampoline_start)
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cli # We should be safe anyway
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wbinvd
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LJMPW_RM(1f)
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1:
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mov %cs, %ax # Code and data in the same place
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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movl $0xA5A5A5A5, trampoline_status
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# write marker for master knows we're running
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# Setup stack
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movl $rm_stack_end, %esp
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call verify_cpu # Verify the cpu supports long mode
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testl %eax, %eax # Check for return code
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jnz no_longmode
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/*
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* GDT tables in non default location kernel can be beyond 16MB and
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* lgdt will not be able to load the address as in real mode default
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* operand size is 16bit. Use lgdtl instead to force operand size
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* to 32 bit.
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*/
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lidtl tr_idt # load idt with 0, 0
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lgdtl tr_gdt # load gdt with whatever is appropriate
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movw $__KERNEL_DS, %dx # Data segment descriptor
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# Enable protected mode
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movl $X86_CR0_PE, %eax # protected mode (PE) bit
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movl %eax, %cr0 # into protected mode
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# flush prefetch and jump to startup_32
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ljmpl $__KERNEL32_CS, $pa_startup_32
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no_longmode:
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hlt
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jmp no_longmode
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#include "../kernel/verify_cpu.S"
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.section ".text32","ax"
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.code32
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.balign 4
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ENTRY(startup_32)
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movl %edx, %ss
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addl $pa_real_mode_base, %esp
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movl %edx, %ds
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movl %edx, %es
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movl %edx, %fs
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movl %edx, %gs
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/*
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* Check for memory encryption support. This is a safety net in
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* case BIOS hasn't done the necessary step of setting the bit in
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* the MSR for this AP. If SME is active and we've gotten this far
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* then it is safe for us to set the MSR bit and continue. If we
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* don't we'll eventually crash trying to execute encrypted
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* instructions.
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*/
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btl $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
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jnc .Ldone
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movl $MSR_K8_SYSCFG, %ecx
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rdmsr
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bts $MSR_K8_SYSCFG_MEM_ENCRYPT_BIT, %eax
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jc .Ldone
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/*
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* Memory encryption is enabled but the SME enable bit for this
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* CPU has has not been set. It is safe to set it, so do so.
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*/
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wrmsr
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.Ldone:
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movl pa_tr_cr4, %eax
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movl %eax, %cr4 # Enable PAE mode
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# Setup trampoline 4 level pagetables
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movl $pa_trampoline_pgd, %eax
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movl %eax, %cr3
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# Set up EFER
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movl pa_tr_efer, %eax
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movl pa_tr_efer + 4, %edx
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movl $MSR_EFER, %ecx
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wrmsr
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# Enable paging and in turn activate Long Mode
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movl $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax
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movl %eax, %cr0
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/*
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* At this point we're in long mode but in 32bit compatibility mode
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* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
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* EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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*/
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ljmpl $__KERNEL_CS, $pa_startup_64
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.section ".text64","ax"
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.code64
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.balign 4
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ENTRY(startup_64)
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# Now jump into the kernel using virtual addresses
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jmpq *tr_start(%rip)
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.section ".rodata","a"
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# Duplicate the global descriptor table
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# so the kernel can live anywhere
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.balign 16
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.globl tr_gdt
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tr_gdt:
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.short tr_gdt_end - tr_gdt - 1 # gdt limit
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.long pa_tr_gdt
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.short 0
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.quad 0x00cf9b000000ffff # __KERNEL32_CS
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.quad 0x00af9b000000ffff # __KERNEL_CS
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.quad 0x00cf93000000ffff # __KERNEL_DS
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tr_gdt_end:
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.bss
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.balign PAGE_SIZE
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GLOBAL(trampoline_pgd) .space PAGE_SIZE
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.balign 8
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GLOBAL(trampoline_header)
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tr_start: .space 8
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GLOBAL(tr_efer) .space 8
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GLOBAL(tr_cr4) .space 4
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GLOBAL(tr_flags) .space 4
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END(trampoline_header)
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#include "trampoline_common.S"
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