Heiko Stuebner 1089737034 clk: rockchip: register pll mux before pll itself ... The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll does have an init callback to make sure the boot-selected frequency is using the expected pll settings and resets the same frequency using the values provided in the driver if necessary. The setting itself also involves remuxing the pll-mux temporarily to the xin24m source to let the new pll rate settle. Until now this worked flawlessly, even when it had the flaw of accessing the mux settings before the mux actually got registered. With the recent clock-core conversions this flaw became apparent in null pointer dereference in [<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8) [<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320) So to fix that, simply register the pll-mux before the pll, so that it will be fully initialized when the pll clock executes its init- callback and possibly touches the pll-mux clock. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>		2015-08-24 16:49:15 -07:00
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clk-cpu.c	clk: rockchip: Properly include clk.h	2015-07-20 11:11:10 -07:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-pll.c	clk: rockchip: register pll mux before pll itself	2015-08-24 16:49:15 -07:00
clk-rk3188.c	clk: rockchip: Fix SPIF special clock definition	2015-08-12 00:59:22 -07:00
clk-rk3288.c	clk: rockchip: Fix PLL bandwidth	2015-07-28 11:59:12 -07:00
clk-rk3368.c	clk: rockchip: add rk3368 clock controller	2015-07-06 15:09:22 -07:00
clk-rockchip.c
clk.c	clk: rockchip: add support for phase inverters	2015-07-06 15:04:40 -07:00
clk.h	clk: rockchip: Fix PLL bandwidth	2015-07-28 11:59:12 -07:00
Makefile	clk: rockchip: add rk3368 clock controller	2015-07-06 15:09:22 -07:00
softrst.c