linux/include/dt-bindings/phy
Kishon Vijay Abraham I 4e0ae876f7 dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC
AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can select from one of the three input clocks.
The right output can select between left input and external reference
clock while the left output can select between the right input and
external reference clock.

The left and right input reference clock of SERDES0 and SERDES1
respectively are connected to the SoC clock. In the case of two lane
SERDES personality card, the left input of SERDES1 is connected to
the right output of SERDES0 in a chained fashion.

See section "Reference Clock Distribution" of AM65x Sitara Processors
TRM (SPRUID7 – April 2018) for more details.

Add dt-binding documentation in order to represent all these different
configurations in device tree.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17 14:13:18 +05:30
..
phy-am654-serdes.h dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC 2019-04-17 14:13:18 +05:30
phy-ocelot-serdes.h dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1 2018-10-22 19:27:14 -07:00
phy-pistachio-usb.h phy: Add binding document for Pistachio USB2.0 PHY 2015-06-21 21:53:37 +02:00
phy-qcom-qusb2.h dt-bindings: phy-qcom-usb2: Add support to override tuning values 2018-05-20 21:51:31 +05:30
phy.h dt-bindings: phy: Add PHY_TYPE_UFS definition 2017-10-23 11:19:27 +05:30