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4d9d54a730
PHY_2LANE bit is always set in DP_PHY_CTRL, breaking 1 lane use. Set PHY_2LANE only when 2 lanes are used. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190103115954.12785-4-tomi.valkeinen@ti.com |
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adv7511 | ||
analogix | ||
synopsys | ||
analogix-anx78xx.c | ||
analogix-anx78xx.h | ||
cdns-dsi.c | ||
dumb-vga-dac.c | ||
Kconfig | ||
lvds-encoder.c | ||
Makefile | ||
megachips-stdpxxxx-ge-b850v3-fw.c | ||
nxp-ptn3460.c | ||
panel.c | ||
parade-ps8622.c | ||
sii902x.c | ||
sii9234.c | ||
sil-sii8620.c | ||
sil-sii8620.h | ||
tc358764.c | ||
tc358767.c | ||
thc63lvd1024.c | ||
ti-sn65dsi86.c | ||
ti-tfp410.c |