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linux/drivers/video
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Ian Abbott 4d4e2c003b video: da8xx-fb: preserve display width when changing HSYNC 
When looking at this driver for a client, I noticed the code that
configures the HSYNC pulse clobbers the display width in the same
register.  It only preserves the MS part of the width in bit 3 and zeros
the LS part of the width in bits 9 to 4.  This doesn't matter during
initialization as the width is configured afterwards, but subsequent use
of the FBIPUT_HSYNC ioctl would clobber the width.

Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the
horizontal sync.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2014-08-26 15:36:51 +03:00
..
backlight ARM: SoC driver changes for 3.17 2014-08-08 11:34:32 -07:00
console Merge tag 'drm-intel-fixes-2014-06-17' of git://anongit.freedesktop.org/drm-intel into drm-next 2014-06-19 10:54:35 +10:00
fbdev video: da8xx-fb: preserve display width when changing HSYNC 2014-08-26 15:36:51 +03:00
logo x86, platforms: Remove SGI Visual Workstation 2014-02-27 08:07:39 -08:00
display_timing.c video: add display_timing and videomode 2013-01-24 09:03:04 +01:00
hdmi.c video/hdmi: Rename HDMI_IDENTIFIER to HDMI_IEEE_OUI 2013-08-30 08:42:01 +10:00
Kconfig gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging 2014-06-04 11:06:52 +02:00
Makefile video: move fbdev to drivers/video/fbdev 2014-04-17 08:10:19 +03:00
of_display_timing.c video: of: display_timing: double free on error 2014-08-26 14:23:47 +03:00
of_videomode.c videomode: videomode_from_timing work 2013-03-21 14:34:33 +02:00
vgastate.c
videomode.c videomode: videomode_from_timing work 2013-03-21 14:34:33 +02:00