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482e75e7b3
The external clock frequency times the PLL multiplier may exceed the value range of 32-bit unsigned integers. Instead perform the same calculation y using two divisions. The result has some potential to be different, but that's ok: this number is used to limit the range of pre-PLL divisors to find optimal values. So the effect of the rare case of a different result here would mean an invalid pre-PLL divisor is tried. That will be found out a little later in any case. Also guard against dividing by zero if the external clock frequency is higher than the maximum OP PLL output clock --- a rather improbable case. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> |
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cec | ||
common | ||
dvb-core | ||
dvb-frontends | ||
firewire | ||
i2c | ||
mc | ||
mmc | ||
pci | ||
platform | ||
radio | ||
rc | ||
spi | ||
test-drivers | ||
tuners | ||
usb | ||
v4l2-core | ||
Kconfig | ||
Makefile |