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XTFPGA boards provides an audio subsystem that consists of TI CDCE706 clock synthesizer, I2S transmitter and TLV320AIC23 audio codec. I2S transmitter has MMIO-based interface that resembles that of the OpenCores I2S transmitter. I2S transmitter is always a master on I2S bus. There's no specialized audio DMA, sample data are transferred to I2S transmitter FIFO by CPU through memory-mapped queue interface. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
19 lines
500 B
Plaintext
19 lines
500 B
Plaintext
Bindings for I2S controller built into xtfpga Xtensa bitstreams.
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Required properties:
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- compatible: shall be "cdns,xtfpga-i2s".
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- reg: memory region (address and length) with device registers.
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- interrupts: interrupt for the device.
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- clocks: phandle to the clk used as master clock. I2S bus clock
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is derived from it.
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Examples:
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i2s0: xtfpga-i2s@0d080000 {
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#sound-dai-cells = <0>;
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compatible = "cdns,xtfpga-i2s";
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reg = <0x0d080000 0x40>;
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interrupts = <2 1>;
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clocks = <&cdce706 4>;
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};
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