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755864feb7
Newer Rockchip socs like the px30 use a different one-time-programmable memory controller for things like cpu-id and leakage information, so add the necessary driver for it. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> [ported from vendor 4.4, converted to clock-bulk API and cleanups] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191029114240.14905-11-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
268 lines
6.3 KiB
C
268 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip OTP Driver
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*
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* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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/* OTP Register Offsets */
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#define OTPC_SBPI_CTRL 0x0020
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#define OTPC_SBPI_CMD_VALID_PRE 0x0024
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#define OTPC_SBPI_CS_VALID_PRE 0x0028
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#define OTPC_SBPI_STATUS 0x002C
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#define OTPC_USER_CTRL 0x0100
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#define OTPC_USER_ADDR 0x0104
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#define OTPC_USER_ENABLE 0x0108
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#define OTPC_USER_Q 0x0124
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#define OTPC_INT_STATUS 0x0304
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#define OTPC_SBPI_CMD0_OFFSET 0x1000
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#define OTPC_SBPI_CMD1_OFFSET 0x1004
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/* OTP Register bits and masks */
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#define OTPC_USER_ADDR_MASK GENMASK(31, 16)
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#define OTPC_USE_USER BIT(0)
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#define OTPC_USE_USER_MASK GENMASK(16, 16)
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#define OTPC_USER_FSM_ENABLE BIT(0)
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#define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
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#define OTPC_SBPI_DONE BIT(1)
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#define OTPC_USER_DONE BIT(2)
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#define SBPI_DAP_ADDR 0x02
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#define SBPI_DAP_ADDR_SHIFT 8
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#define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
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#define SBPI_CMD_VALID_MASK GENMASK(31, 16)
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#define SBPI_DAP_CMD_WRF 0xC0
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#define SBPI_DAP_REG_ECC 0x3A
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#define SBPI_ECC_ENABLE 0x00
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#define SBPI_ECC_DISABLE 0x09
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#define SBPI_ENABLE BIT(0)
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#define SBPI_ENABLE_MASK GENMASK(16, 16)
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#define OTPC_TIMEOUT 10000
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struct rockchip_otp {
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struct device *dev;
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void __iomem *base;
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struct clk_bulk_data *clks;
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int num_clks;
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struct reset_control *rst;
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};
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/* list of required clocks */
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static const char * const rockchip_otp_clocks[] = {
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"otp", "apb_pclk", "phy",
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};
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struct rockchip_data {
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int size;
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};
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static int rockchip_otp_reset(struct rockchip_otp *otp)
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{
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int ret;
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ret = reset_control_assert(otp->rst);
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if (ret) {
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dev_err(otp->dev, "failed to assert otp phy %d\n", ret);
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return ret;
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}
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udelay(2);
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ret = reset_control_deassert(otp->rst);
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if (ret) {
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dev_err(otp->dev, "failed to deassert otp phy %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
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{
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u32 status = 0;
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int ret;
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ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
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(status & flag), 1, OTPC_TIMEOUT);
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if (ret)
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return ret;
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/* clean int status */
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writel(flag, otp->base + OTPC_INT_STATUS);
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return 0;
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}
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static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
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{
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int ret = 0;
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writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
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otp->base + OTPC_SBPI_CTRL);
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writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
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writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
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otp->base + OTPC_SBPI_CMD0_OFFSET);
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if (enable)
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writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
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else
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writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
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writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
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ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
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if (ret < 0)
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dev_err(otp->dev, "timeout during ecc_enable\n");
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return ret;
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}
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static int rockchip_otp_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct rockchip_otp *otp = context;
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u8 *buf = val;
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int ret = 0;
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ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
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if (ret < 0) {
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dev_err(otp->dev, "failed to prepare/enable clks\n");
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return ret;
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}
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ret = rockchip_otp_reset(otp);
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if (ret) {
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dev_err(otp->dev, "failed to reset otp phy\n");
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goto disable_clks;
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}
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ret = rockchip_otp_ecc_enable(otp, false);
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if (ret < 0) {
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dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
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goto disable_clks;
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}
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writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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udelay(5);
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while (bytes--) {
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writel(offset++ | OTPC_USER_ADDR_MASK,
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otp->base + OTPC_USER_ADDR);
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writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
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otp->base + OTPC_USER_ENABLE);
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ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
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if (ret < 0) {
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dev_err(otp->dev, "timeout during read setup\n");
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goto read_end;
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}
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*buf++ = readb(otp->base + OTPC_USER_Q);
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}
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read_end:
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writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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disable_clks:
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clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
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return ret;
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}
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static struct nvmem_config otp_config = {
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.name = "rockchip-otp",
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.owner = THIS_MODULE,
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.read_only = true,
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.stride = 1,
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.word_size = 1,
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.reg_read = rockchip_otp_read,
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};
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static const struct rockchip_data px30_data = {
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.size = 0x40,
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};
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static const struct of_device_id rockchip_otp_match[] = {
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{
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.compatible = "rockchip,px30-otp",
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.data = (void *)&px30_data,
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},
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{
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.compatible = "rockchip,rk3308-otp",
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.data = (void *)&px30_data,
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_otp_match);
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static int rockchip_otp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_otp *otp;
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const struct rockchip_data *data;
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struct nvmem_device *nvmem;
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int ret, i;
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data = of_device_get_match_data(dev);
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if (!data) {
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dev_err(dev, "failed to get match data\n");
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return -EINVAL;
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}
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otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
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GFP_KERNEL);
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if (!otp)
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return -ENOMEM;
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otp->dev = dev;
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otp->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(otp->base))
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return PTR_ERR(otp->base);
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otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks);
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otp->clks = devm_kcalloc(dev, otp->num_clks,
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sizeof(*otp->clks), GFP_KERNEL);
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if (!otp->clks)
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return -ENOMEM;
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for (i = 0; i < otp->num_clks; ++i)
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otp->clks[i].id = rockchip_otp_clocks[i];
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ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
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if (ret)
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return ret;
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otp->rst = devm_reset_control_get(dev, "phy");
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if (IS_ERR(otp->rst))
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return PTR_ERR(otp->rst);
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otp_config.size = data->size;
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otp_config.priv = otp;
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otp_config.dev = dev;
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nvmem = devm_nvmem_register(dev, &otp_config);
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return PTR_ERR_OR_ZERO(nvmem);
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}
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static struct platform_driver rockchip_otp_driver = {
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.probe = rockchip_otp_probe,
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.driver = {
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.name = "rockchip-otp",
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.of_match_table = rockchip_otp_match,
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},
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};
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module_platform_driver(rockchip_otp_driver);
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MODULE_DESCRIPTION("Rockchip OTP driver");
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MODULE_LICENSE("GPL v2");
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