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External IRQ0 (index 48) has the same capabilities as the other IRQ1-7 and is handled by the same register IPIC_SEPNR. When this register is not specified for "ack" in "ipic_info", you cannot configure this IRQ as IRQ_TYPE_EDGE_FALLING. This oversight was probably due to the non-contiguous hwirq numbering of IRQ0 in the IPIC. Signed-off-by: Jurgen Schindele <schindele@nentec.de> [scottwood: Cleaned up commit message and posted as a proper patch] Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
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| .. | ||
| ge | ||
| xics | ||
| xive | ||
| 6xx-suspend.S | ||
| axonram.c | ||
| cpm1.c | ||
| cpm2.c | ||
| cpm2_pic.c | ||
| cpm2_pic.h | ||
| cpm_common.c | ||
| dart.h | ||
| dart_iommu.c | ||
| dcr-low.S | ||
| dcr.c | ||
| ehv_pic.c | ||
| fsl_85xx_cache_ctlr.h | ||
| fsl_85xx_cache_sram.c | ||
| fsl_85xx_l2ctlr.c | ||
| fsl_gtm.c | ||
| fsl_lbc.c | ||
| fsl_mpic_err.c | ||
| fsl_mpic_timer_wakeup.c | ||
| fsl_msi.c | ||
| fsl_msi.h | ||
| fsl_pci.c | ||
| fsl_pci.h | ||
| fsl_pmc.c | ||
| fsl_rcpm.c | ||
| fsl_rio.c | ||
| fsl_rio.h | ||
| fsl_rmu.c | ||
| fsl_soc.c | ||
| fsl_soc.h | ||
| grackle.c | ||
| i8259.c | ||
| indirect_pci.c | ||
| ipic.c | ||
| ipic.h | ||
| Kconfig | ||
| Makefile | ||
| micropatch.c | ||
| mmio_nvram.c | ||
| mpc5xxx_clocks.c | ||
| mpc8xx_pic.c | ||
| mpc8xx_pic.h | ||
| mpic.c | ||
| mpic.h | ||
| mpic_msgr.c | ||
| mpic_msi.c | ||
| mpic_timer.c | ||
| mpic_u3msi.c | ||
| msi_bitmap.c | ||
| mv64x60.h | ||
| mv64x60_dev.c | ||
| mv64x60_pci.c | ||
| mv64x60_pic.c | ||
| mv64x60_udbg.c | ||
| of_rtc.c | ||
| pmi.c | ||
| ppc4xx_cpm.c | ||
| ppc4xx_gpio.c | ||
| ppc4xx_hsta_msi.c | ||
| ppc4xx_msi.c | ||
| ppc4xx_ocm.c | ||
| ppc4xx_pci.c | ||
| ppc4xx_pci.h | ||
| ppc4xx_soc.c | ||
| rtc_cmos_setup.c | ||
| scom.c | ||
| simple_gpio.c | ||
| simple_gpio.h | ||
| tsi108_dev.c | ||
| tsi108_pci.c | ||
| udbg_memcons.c | ||
| uic.c | ||
| xilinx_intc.c | ||
| xilinx_pci.c | ||