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On systems running with virtual cpus there is optimization potential in regard to spinlocks and rw-locks. If the virtual cpu that has taken a lock is known to a cpu that wants to acquire the same lock it is beneficial to yield the timeslice of the virtual cpu in favour of the cpu that has the lock (directed yield). With CONFIG_PREEMPT="n" this can be implemented by the architecture without common code changes. Powerpc already does this. With CONFIG_PREEMPT="y" the lock loops are coded with _raw_spin_trylock, _raw_read_trylock and _raw_write_trylock in kernel/spinlock.c. If the lock could not be taken cpu_relax is called. A directed yield is not possible because cpu_relax doesn't know anything about the lock. To be able to yield the lock in favour of the current lock holder variants of cpu_relax for spinlocks and rw-locks are needed. The new _raw_spin_relax, _raw_read_relax and _raw_write_relax primitives differ from cpu_relax insofar that they have an argument: a pointer to the lock structure. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Paul Mackerras <paulus@samba.org> Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
167 lines
4 KiB
C
167 lines
4 KiB
C
/* spinlock.h: 32-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC_SPINLOCK_H
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#define __SPARC_SPINLOCK_H
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#include <linux/threads.h> /* For NR_CPUS */
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#ifndef __ASSEMBLY__
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#include <asm/psr.h>
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#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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"\n1:\n\t"
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"ldstub [%0], %%g2\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2f\n\t"
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" ldub [%0], %%g2\n\t"
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".subsection 2\n"
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"2:\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2b\n\t"
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" ldub [%0], %%g2\n\t"
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"b,a 1b\n\t"
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".previous\n"
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: /* no outputs */
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: "r" (lock)
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: "g2", "memory", "cc");
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned int result;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0);
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
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}
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/* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* XXX This might create some problems with my dual spinlock
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* XXX scheme, deadlocks etc. -DaveM
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*
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* Sort of like atomic_t's on Sparc, but even more clever.
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*
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* ------------------------------------
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* | 24-bit counter | wlock | raw_rwlock_t
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* ------------------------------------
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* 31 8 7 0
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*
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* wlock signifies the one writer is in or somebody is updating
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* counter. For a writer, if he successfully acquires the wlock,
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* but counter is non-zero, he has to release the lock and wait,
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* till both counter and wlock are zero.
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*
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* Unfortunately this scheme limits us to ~16,000,000 cpus.
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*/
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static inline void __read_lock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define __raw_read_lock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__read_lock(lock); \
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local_irq_restore(flags); \
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} while(0)
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static inline void __read_unlock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_exit\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define __raw_read_unlock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__read_unlock(lock); \
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local_irq_restore(flags); \
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} while(0)
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_write_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned int val;
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__asm__ __volatile__("ldstub [%1 + 3], %0"
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: "=r" (val)
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: "r" (&rw->lock)
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: "memory");
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if (val == 0) {
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val = rw->lock & ~0xff;
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if (val)
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((volatile u8*)&rw->lock)[3] = 0;
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}
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return (val == 0);
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}
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#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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#endif /* !(__ASSEMBLY__) */
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#endif /* __SPARC_SPINLOCK_H */
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