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SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
36 lines
1,012 B
C
36 lines
1,012 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
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/* Clocks */
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#define VIDEO_CC_AHB_CLK_SRC 0
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#define VIDEO_CC_MVS0_CLK 1
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#define VIDEO_CC_MVS0_CLK_SRC 2
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#define VIDEO_CC_MVS0_DIV_CLK_SRC 3
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#define VIDEO_CC_MVS0C_CLK 4
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#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 5
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#define VIDEO_CC_MVS1_CLK 6
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#define VIDEO_CC_MVS1_CLK_SRC 7
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#define VIDEO_CC_MVS1_DIV2_CLK 8
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#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
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#define VIDEO_CC_MVS1C_CLK 10
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#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
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#define VIDEO_CC_SLEEP_CLK 12
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#define VIDEO_CC_SLEEP_CLK_SRC 13
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#define VIDEO_CC_XO_CLK_SRC 14
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#define VIDEO_PLL0 15
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#define VIDEO_PLL1 16
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/* GDSCs */
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#define MVS0C_GDSC 0
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#define MVS1C_GDSC 1
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#define MVS0_GDSC 2
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#define MVS1_GDSC 3
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#endif
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