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b3f9581aff
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Copyright (c) 2016 Krzysztof Kozlowski
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*
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* Device Tree binding constants for Exynos5421 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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/* core clocks */
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#define CLK_FIN_PLL 1
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#define CLK_FOUT_APLL 2
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#define CLK_FOUT_CPLL 3
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#define CLK_FOUT_MPLL 4
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#define CLK_FOUT_BPLL 5
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#define CLK_FOUT_KPLL 6
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#define CLK_FOUT_EPLL 7
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_UART0 128
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#define CLK_SCLK_UART1 129
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#define CLK_SCLK_UART2 130
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#define CLK_SCLK_UART3 131
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#define CLK_SCLK_MMC0 132
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#define CLK_SCLK_MMC1 133
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#define CLK_SCLK_MMC2 134
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#define CLK_SCLK_USBD300 150
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#define CLK_SCLK_USBD301 151
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#define CLK_SCLK_USBPHY300 152
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#define CLK_SCLK_USBPHY301 153
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#define CLK_SCLK_PWM 155
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/* gate clocks */
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#define CLK_UART0 257
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#define CLK_UART1 258
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#define CLK_UART2 259
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#define CLK_UART3 260
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#define CLK_I2C0 261
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#define CLK_I2C1 262
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#define CLK_I2C2 263
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#define CLK_I2C3 264
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#define CLK_USI0 265
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#define CLK_USI1 266
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#define CLK_USI2 267
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#define CLK_USI3 268
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#define CLK_TSADC 270
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#define CLK_PWM 279
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#define CLK_MCT 315
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#define CLK_WDT 316
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#define CLK_RTC 317
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#define CLK_TMU 318
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#define CLK_MMC0 351
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#define CLK_MMC1 352
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#define CLK_MMC2 353
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#define CLK_PDMA0 362
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#define CLK_PDMA1 363
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#define CLK_USBH20 365
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#define CLK_USBD300 366
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#define CLK_USBD301 367
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#define CLK_SSS 471
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
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