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416912a129
The GPIO pins select which sub bus is connected to the master. Initially tested with an sn74cbtlv3253 switch device wired into the MDIO bus. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
128 lines
3.2 KiB
Plaintext
128 lines
3.2 KiB
Plaintext
Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
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This is a special case of a MDIO bus multiplexer. One or more GPIO
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lines are used to control which child bus is connected.
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Required properties in addition to the generic multiplexer properties:
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- compatible : mdio-mux-gpio.
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- gpios : GPIO specifiers for each GPIO line. One or more must be specified.
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Example :
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/* The parent MDIO bus. */
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smi1: mdio@1180000001900 {
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compatible = "cavium,octeon-3860-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11800 0x00001900 0x0 0x40>;
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};
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/*
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
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pair of GPIO lines. Child busses 2 and 3 populated with 4
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PHYs each.
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*/
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mdio-mux {
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compatible = "mdio-mux-gpio";
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gpios = <&gpio1 3 0>, <&gpio1 4 0>;
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mdio-parent-bus = <&smi1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy11: ethernet-phy@1 {
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reg = <1>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy12: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy13: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy14: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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};
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mdio@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy21: ethernet-phy@1 {
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reg = <1>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy22: ethernet-phy@2 {
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reg = <2>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy23: ethernet-phy@3 {
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reg = <3>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy24: ethernet-phy@4 {
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reg = <4>;
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compatible = "marvell,88e1149r";
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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};
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