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6dbc002970
The CPU PMU code is tightly coupled with generic ARM PMU handling code. This makes it cumbersome when trying to add support for other ARM PMUs (e.g. interconnect, L2 cache controller, bus) as the generic parts of the code are not readily reusable. This patch cleans up perf_event.c so that reusable code is exposed via header files to other potential PMU drivers. The CPU code is consistently named to identify it as such and also to prepare for moving it into a separate file. Signed-off-by: Will Deacon <will.deacon@arm.com>
25 lines
606 B
C
25 lines
606 B
C
/*
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* linux/arch/arm/include/asm/perf_event.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PERF_EVENT_H__
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#define __ARM_PERF_EVENT_H__
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/*
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* The ARMv7 CPU PMU supports up to 32 event counters.
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*/
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#define ARMPMU_MAX_HWEVENTS 32
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#define HW_OP_UNSUPPORTED 0xFFFF
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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#endif /* __ARM_PERF_EVENT_H__ */
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