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5c69177df4
These patches modify the common probe routine to recognize the RTL8188EE chip and implement asynchronous firmware reading in the callback routine to initialize the sw variables. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: jcheung@suse.com Cc: machen@suse.com Cc: mmarek@suse.cz Cc: zhiyuan_yang@realsil.com.cn Cc: page_he@realsil.com.cn Signed-off-by: John W. Linville <linville@tuxdriver.com>
281 lines
7.3 KiB
C
281 lines
7.3 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL_PCI_H__
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#define __RTL_PCI_H__
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#include <linux/pci.h>
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/*
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1: MSDU packet queue,
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2: Rx Command Queue
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*/
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#define RTL_PCI_RX_MPDU_QUEUE 0
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#define RTL_PCI_RX_CMD_QUEUE 1
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#define RTL_PCI_MAX_RX_QUEUE 2
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#define RTL_PCI_MAX_RX_COUNT 64
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#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
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#define RT_TXDESC_NUM 128
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#define RT_TXDESC_NUM_BE_QUEUE 256
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#define BK_QUEUE 0
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#define BE_QUEUE 1
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#define VI_QUEUE 2
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#define VO_QUEUE 3
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#define BEACON_QUEUE 4
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#define TXCMD_QUEUE 5
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#define MGNT_QUEUE 6
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#define HIGH_QUEUE 7
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#define HCCA_QUEUE 8
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#define RTL_PCI_DEVICE(vend, dev, cfg) \
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.vendor = (vend), \
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.device = (dev), \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID,\
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.driver_data = (kernel_ulong_t)&(cfg)
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#define PCI_MAX_BRIDGE_NUMBER 255
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
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#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
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#define U1DONTCARE 0xFF
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#define U2DONTCARE 0xFFFF
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#define U4DONTCARE 0xFFFFFFFF
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#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
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#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
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#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
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#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
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#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
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#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
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#define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
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#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
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#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
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#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
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#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
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#define RTL_PCI_700F_DID 0x700F
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#define RTL_PCI_701F_DID 0x701F
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#define RTL_PCI_DLINK_DID 0x3304
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#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
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#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
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#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
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#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
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#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
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#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
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#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
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#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
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/*8192 support 16 pages of IO registers*/
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#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
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#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
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#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
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#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
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#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
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#define RTL_PCI_REVISION_ID_8190PCI 0x00
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#define RTL_PCI_REVISION_ID_8192PCIE 0x01
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#define RTL_PCI_REVISION_ID_8192SE 0x10
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#define RTL_PCI_REVISION_ID_8192CE 0x1
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#define RTL_PCI_REVISION_ID_8192DE 0x0
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#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
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enum pci_bridge_vendor {
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PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
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PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
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PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
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PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
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PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
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PCI_BRIDGE_VENDOR_MAX,
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};
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struct rtl_pci_capabilities_header {
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u8 capability_id;
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u8 next;
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};
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struct rtl_rx_desc {
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u32 dword[8];
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} __packed;
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struct rtl_tx_desc {
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u32 dword[16];
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} __packed;
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struct rtl_tx_cmd_desc {
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u32 dword[16];
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} __packed;
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struct rtl8192_tx_ring {
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struct rtl_tx_desc *desc;
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dma_addr_t dma;
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unsigned int idx;
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unsigned int entries;
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struct sk_buff_head queue;
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};
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struct rtl8192_rx_ring {
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struct rtl_rx_desc *desc;
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dma_addr_t dma;
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unsigned int idx;
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struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
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};
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struct rtl_pci {
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struct pci_dev *pdev;
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bool irq_enabled;
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bool driver_is_goingto_unload;
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bool up_first_time;
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bool first_init;
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bool being_init_adapter;
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bool init_ready;
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/*Tx */
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struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
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int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
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u32 transmit_config;
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/*Rx */
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struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
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int rxringcount;
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u16 rxbuffersize;
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u32 receive_config;
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/*irq */
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u8 irq_alloc;
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u32 irq_mask[2];
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u32 sys_irq_mask;
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/*Bcn control register setting */
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u32 reg_bcn_ctrl_val;
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/*ASPM*/ u8 const_pci_aspm;
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u8 const_amdpci_aspm;
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u8 const_hwsw_rfoff_d3;
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u8 const_support_pciaspm;
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/*pci-e bridge */
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u8 const_hostpci_aspm_setting;
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/*pci-e device */
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u8 const_devicepci_aspm_setting;
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/*If it supports ASPM, Offset[560h] = 0x40,
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otherwise Offset[560h] = 0x00. */
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bool support_aspm;
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bool support_backdoor;
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/*QOS & EDCA */
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enum acm_method acm_method;
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u16 shortretry_limit;
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u16 longretry_limit;
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};
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struct mp_adapter {
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u8 linkctrl_reg;
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u8 busnumber;
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u8 devnumber;
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u8 funcnumber;
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u8 pcibridge_busnum;
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u8 pcibridge_devnum;
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u8 pcibridge_funcnum;
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u8 pcibridge_vendor;
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u16 pcibridge_vendorid;
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u16 pcibridge_deviceid;
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u8 num4bytes;
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u8 pcibridge_pciehdr_offset;
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u8 pcibridge_linkctrlreg;
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bool amd_l1_patch;
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};
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struct rtl_pci_priv {
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struct rtl_pci dev;
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struct mp_adapter ndis_adapter;
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struct rtl_led_ctl ledctl;
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struct bt_coexist_info bt_coexist;
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};
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#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
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#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
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int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
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extern struct rtl_intf_ops rtl_pci_ops;
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int rtl_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id);
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void rtl_pci_disconnect(struct pci_dev *pdev);
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#ifdef CONFIG_PM_SLEEP
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int rtl_pci_suspend(struct device *dev);
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int rtl_pci_resume(struct device *dev);
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#endif /* CONFIG_PM_SLEEP */
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static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
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{
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return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
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{
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return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
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{
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return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
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{
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writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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static inline void pci_write16_async(struct rtl_priv *rtlpriv,
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u32 addr, u16 val)
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{
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writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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static inline void pci_write32_async(struct rtl_priv *rtlpriv,
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u32 addr, u32 val)
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{
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writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
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}
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#endif
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