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3f7c01ade2
This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> |
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| .. | ||
| clk | ||
| clock | ||
| dma | ||
| gpio | ||
| input | ||
| interrupt-controller | ||
| mfd | ||
| pinctrl | ||
| pwm | ||
| reset | ||
| reset-controller | ||
| sound | ||
| spmi | ||
| thermal | ||