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3d9dd6fdd2
The EMC driver needs to know the number of external memory devices and also needs to update the EMEM configuration based on the new rate of the memory bus. To know how to update the EMEM config, looks up the values of the burst regs in the DT, for a given timing. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
438 lines
10 KiB
C
438 lines
10 KiB
C
/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/sort.h>
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#include <soc/tegra/fuse.h>
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#include "mc.h"
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#define MC_INTSTATUS 0x000
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#define MC_INT_DECERR_MTS (1 << 16)
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#define MC_INT_SECERR_SEC (1 << 13)
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#define MC_INT_DECERR_VPR (1 << 12)
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#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
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#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
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#define MC_INT_ARBITRATION_EMEM (1 << 9)
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#define MC_INT_SECURITY_VIOLATION (1 << 8)
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#define MC_INT_DECERR_EMEM (1 << 6)
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#define MC_INTMASK 0x004
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#define MC_ERR_STATUS 0x08
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#define MC_ERR_STATUS_TYPE_SHIFT 28
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#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
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#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
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#define MC_ERR_STATUS_READABLE (1 << 27)
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#define MC_ERR_STATUS_WRITABLE (1 << 26)
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#define MC_ERR_STATUS_NONSECURE (1 << 25)
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#define MC_ERR_STATUS_ADR_HI_SHIFT 20
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#define MC_ERR_STATUS_ADR_HI_MASK 0x3
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#define MC_ERR_STATUS_SECURITY (1 << 17)
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#define MC_ERR_STATUS_RW (1 << 16)
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#define MC_ERR_STATUS_CLIENT_MASK 0x7f
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#define MC_ERR_ADR 0x0c
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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#define MC_EMEM_ARB_MISC0 0xd8
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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static const struct of_device_id tegra_mc_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
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#endif
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
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static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
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{
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unsigned long long tick;
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unsigned int i;
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u32 value;
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/* compute the number of MC clock cycles per tick */
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tick = mc->tick * clk_get_rate(mc->clk);
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do_div(tick, NSEC_PER_SEC);
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value = readl(mc->regs + MC_EMEM_ARB_CFG);
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value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
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value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
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writel(value, mc->regs + MC_EMEM_ARB_CFG);
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/* write latency allowance defaults */
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for (i = 0; i < mc->soc->num_clients; i++) {
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const struct tegra_mc_la *la = &mc->soc->clients[i].la;
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u32 value;
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value = readl(mc->regs + la->reg);
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value &= ~(la->mask << la->shift);
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value |= (la->def & la->mask) << la->shift;
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writel(value, mc->regs + la->reg);
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}
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return 0;
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}
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void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
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{
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unsigned int i;
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struct tegra_mc_timing *timing = NULL;
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for (i = 0; i < mc->num_timings; i++) {
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if (mc->timings[i].rate == rate) {
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timing = &mc->timings[i];
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break;
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}
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}
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if (!timing) {
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dev_err(mc->dev, "no memory timing registered for rate %lu\n",
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rate);
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return;
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}
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for (i = 0; i < mc->soc->num_emem_regs; ++i)
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mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
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}
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unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
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{
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u8 dram_count;
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dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
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dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
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dram_count++;
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return dram_count;
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}
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static int load_one_timing(struct tegra_mc *mc,
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struct tegra_mc_timing *timing,
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struct device_node *node)
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{
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int err;
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u32 tmp;
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err = of_property_read_u32(node, "clock-frequency", &tmp);
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if (err) {
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dev_err(mc->dev,
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"timing %s: failed to read rate\n", node->name);
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return err;
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}
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timing->rate = tmp;
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timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
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sizeof(u32), GFP_KERNEL);
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if (!timing->emem_data)
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return -ENOMEM;
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err = of_property_read_u32_array(node, "nvidia,emem-configuration",
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timing->emem_data,
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mc->soc->num_emem_regs);
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if (err) {
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dev_err(mc->dev,
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"timing %s: failed to read EMEM configuration\n",
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node->name);
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return err;
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}
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return 0;
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}
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static int load_timings(struct tegra_mc *mc, struct device_node *node)
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{
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struct device_node *child;
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struct tegra_mc_timing *timing;
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int child_count = of_get_child_count(node);
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int i = 0, err;
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mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
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GFP_KERNEL);
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if (!mc->timings)
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return -ENOMEM;
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mc->num_timings = child_count;
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for_each_child_of_node(node, child) {
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timing = &mc->timings[i++];
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err = load_one_timing(mc, timing, child);
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if (err)
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return err;
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}
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return 0;
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}
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static int tegra_mc_setup_timings(struct tegra_mc *mc)
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{
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struct device_node *node;
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u32 ram_code, node_ram_code;
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int err;
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ram_code = tegra_read_ram_code();
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mc->num_timings = 0;
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for_each_child_of_node(mc->dev->of_node, node) {
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err = of_property_read_u32(node, "nvidia,ram-code",
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&node_ram_code);
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if (err || (node_ram_code != ram_code)) {
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of_node_put(node);
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continue;
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}
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err = load_timings(mc, node);
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if (err)
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return err;
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of_node_put(node);
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break;
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}
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if (mc->num_timings == 0)
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dev_warn(mc->dev,
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"no memory timings for RAM code %u registered\n",
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ram_code);
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return 0;
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}
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static const char *const status_names[32] = {
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[ 1] = "External interrupt",
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[ 6] = "EMEM address decode error",
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[ 8] = "Security violation",
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[ 9] = "EMEM arbitration error",
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[10] = "Page fault",
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[11] = "Invalid APB ASID update",
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[12] = "VPR violation",
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[13] = "Secure carveout violation",
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[16] = "MTS carveout violation",
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};
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static const char *const error_names[8] = {
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[2] = "EMEM decode error",
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[3] = "TrustZone violation",
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[4] = "Carveout violation",
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[6] = "SMMU translation error",
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};
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static irqreturn_t tegra_mc_irq(int irq, void *data)
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{
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struct tegra_mc *mc = data;
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unsigned long status, mask;
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unsigned int bit;
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/* mask all interrupts to avoid flooding */
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status = mc_readl(mc, MC_INTSTATUS);
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mask = mc_readl(mc, MC_INTMASK);
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for_each_set_bit(bit, &status, 32) {
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const char *error = status_names[bit] ?: "unknown";
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const char *client = "unknown", *desc;
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const char *direction, *secure;
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phys_addr_t addr = 0;
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unsigned int i;
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char perm[7];
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u8 id, type;
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u32 value;
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value = mc_readl(mc, MC_ERR_STATUS);
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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if (mc->soc->num_address_bits > 32) {
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addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
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MC_ERR_STATUS_ADR_HI_MASK);
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addr <<= 32;
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}
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#endif
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if (value & MC_ERR_STATUS_RW)
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direction = "write";
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else
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direction = "read";
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if (value & MC_ERR_STATUS_SECURITY)
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secure = "secure ";
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else
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secure = "";
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id = value & MC_ERR_STATUS_CLIENT_MASK;
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for (i = 0; i < mc->soc->num_clients; i++) {
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if (mc->soc->clients[i].id == id) {
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client = mc->soc->clients[i].name;
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break;
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}
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}
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type = (value & MC_ERR_STATUS_TYPE_MASK) >>
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MC_ERR_STATUS_TYPE_SHIFT;
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desc = error_names[type];
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switch (value & MC_ERR_STATUS_TYPE_MASK) {
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case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
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perm[0] = ' ';
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perm[1] = '[';
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if (value & MC_ERR_STATUS_READABLE)
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perm[2] = 'R';
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else
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perm[2] = '-';
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if (value & MC_ERR_STATUS_WRITABLE)
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perm[3] = 'W';
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else
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perm[3] = '-';
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if (value & MC_ERR_STATUS_NONSECURE)
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perm[4] = '-';
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else
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perm[4] = 'S';
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perm[5] = ']';
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perm[6] = '\0';
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break;
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default:
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perm[0] = '\0';
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break;
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}
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value = mc_readl(mc, MC_ERR_ADR);
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addr |= value;
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dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
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client, secure, direction, &addr, error,
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desc, perm);
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}
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/* clear interrupts */
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mc_writel(mc, status, MC_INTSTATUS);
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return IRQ_HANDLED;
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}
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static int tegra_mc_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct resource *res;
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struct tegra_mc *mc;
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u32 value;
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int err;
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match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
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if (!match)
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return -ENODEV;
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mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
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if (!mc)
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return -ENOMEM;
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platform_set_drvdata(pdev, mc);
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mc->soc = match->data;
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mc->dev = &pdev->dev;
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/* length of MC tick in nanoseconds */
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mc->tick = 30;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mc->regs))
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return PTR_ERR(mc->regs);
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mc->clk = devm_clk_get(&pdev->dev, "mc");
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if (IS_ERR(mc->clk)) {
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dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
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PTR_ERR(mc->clk));
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return PTR_ERR(mc->clk);
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}
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err = tegra_mc_setup_latency_allowance(mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
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err);
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return err;
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}
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err = tegra_mc_setup_timings(mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
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return err;
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}
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if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
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mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
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if (IS_ERR(mc->smmu)) {
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dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
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PTR_ERR(mc->smmu));
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return PTR_ERR(mc->smmu);
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}
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}
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mc->irq = platform_get_irq(pdev, 0);
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if (mc->irq < 0) {
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dev_err(&pdev->dev, "interrupt not specified\n");
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return mc->irq;
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}
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err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
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dev_name(&pdev->dev), mc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
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err);
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return err;
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}
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value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
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MC_INT_ARBITRATION_EMEM | MC_INT_SECURITY_VIOLATION |
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MC_INT_DECERR_EMEM;
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mc_writel(mc, value, MC_INTMASK);
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return 0;
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}
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static struct platform_driver tegra_mc_driver = {
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.driver = {
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.name = "tegra-mc",
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.of_match_table = tegra_mc_of_match,
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.suppress_bind_attrs = true,
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},
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.prevent_deferred_probe = true,
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.probe = tegra_mc_probe,
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};
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static int tegra_mc_init(void)
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{
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return platform_driver_register(&tegra_mc_driver);
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}
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arch_initcall(tegra_mc_init);
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MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
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MODULE_LICENSE("GPL v2");
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