mirror of
https://github.com/torvalds/linux
synced 2024-09-22 03:55:39 +00:00
3b94ce7b7b
While the resources enumerated by the CEDT.CFMWS identify a cxl_port with host bridges as downstream ports, host bridges themselves are upstream ports that decode to downstream ports represented by PCIe Root Ports. Walk the PCIe Root Ports connected to a CXL Host Bridge, identified by the ACPI0016 _HID, and add each one as a cxl_dport of the host bridge cxl_port. For now, component registers are not enumerated, only the first order uport / dport relationships. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162325451145.2293126.10149150938788969381.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
||
|---|---|---|
| .. | ||
| acpi.c | ||
| core.c | ||
| cxl.h | ||
| Kconfig | ||
| Makefile | ||
| mem.h | ||
| pci.c | ||
| pci.h | ||