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02985b9463
The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
50 lines
1.3 KiB
Plaintext
50 lines
1.3 KiB
Plaintext
Freescale i.MX System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,<chip>-src"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
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in this order.
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- #reset-cells: 1, see below
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example:
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src: src@020d8000 {
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compatible = "fsl,imx6q-src";
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reg = <0x020d8000 0x4000>;
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interrupts = <0 91 0x04 0 96 0x04>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The system reset controller can be used to reset the GPU, VPU,
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IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
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nodes should specify the reset line on the SRC in their resets
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property, containing a phandle to the SRC device node and a
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RESET_INDEX specifying which module to reset, as described in
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reset.txt
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example:
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ipu1: ipu@02400000 {
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resets = <&src 2>;
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};
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ipu2: ipu@02800000 {
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resets = <&src 4>;
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};
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The following RESET_INDEX values are valid for i.MX5:
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GPU_RESET 0
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VPU_RESET 1
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IPU1_RESET 2
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OPEN_VG_RESET 3
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The following additional RESET_INDEX value is valid for i.MX6:
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IPU2_RESET 4
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