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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define CPU_PROCESS_CORNERS 2
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#define GPU_PROCESS_CORNERS 2
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#define SOC_PROCESS_CORNERS 2
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#define FUSE_CPU_SPEEDO_0 0x14
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#define FUSE_CPU_SPEEDO_1 0x2c
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#define FUSE_CPU_SPEEDO_2 0x30
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#define FUSE_SOC_SPEEDO_0 0x34
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#define FUSE_SOC_SPEEDO_1 0x38
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#define FUSE_SOC_SPEEDO_2 0x3c
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#define FUSE_CPU_IDDQ 0x18
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#define FUSE_SOC_IDDQ 0x40
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#define FUSE_GPU_IDDQ 0x128
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#define FUSE_FT_REV 0x28
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
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{2190, UINT_MAX},
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{0, UINT_MAX},
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};
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static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
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{1965, UINT_MAX},
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{0, UINT_MAX},
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};
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static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
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{2101, UINT_MAX},
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{0, UINT_MAX},
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};
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static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
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int *threshold)
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{
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int sku = sku_info->sku_id;
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/* Assign to default */
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sku_info->cpu_speedo_id = 0;
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sku_info->soc_speedo_id = 0;
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sku_info->gpu_speedo_id = 0;
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*threshold = THRESHOLD_INDEX_0;
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switch (sku) {
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case 0x00: /* Eng sku */
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case 0x0F:
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case 0x23:
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/* Using the default */
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break;
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case 0x83:
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sku_info->cpu_speedo_id = 2;
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break;
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case 0x1F:
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case 0x87:
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case 0x27:
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sku_info->cpu_speedo_id = 2;
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sku_info->soc_speedo_id = 0;
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sku_info->gpu_speedo_id = 1;
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*threshold = THRESHOLD_INDEX_0;
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break;
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case 0x81:
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case 0x21:
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case 0x07:
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sku_info->cpu_speedo_id = 1;
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sku_info->soc_speedo_id = 1;
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sku_info->gpu_speedo_id = 1;
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*threshold = THRESHOLD_INDEX_1;
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break;
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case 0x49:
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case 0x4A:
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case 0x48:
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sku_info->cpu_speedo_id = 4;
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sku_info->soc_speedo_id = 2;
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sku_info->gpu_speedo_id = 3;
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*threshold = THRESHOLD_INDEX_1;
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break;
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default:
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pr_err("Tegra Unknown SKU %d\n", sku);
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/* Using the default for the error case */
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break;
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}
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}
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void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info)
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{
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int i, threshold, cpu_speedo_0_value, soc_speedo_0_value;
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int cpu_iddq_value, gpu_iddq_value, soc_iddq_value;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
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/* GPU Speedo is stored in CPU_SPEEDO_2 */
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sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
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soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
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cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
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soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ);
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gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ);
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sku_info->cpu_speedo_value = cpu_speedo_0_value;
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if (sku_info->cpu_speedo_value == 0) {
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pr_warn("Tegra Warning: Speedo value not fused.\n");
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WARN_ON(1);
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return;
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}
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rev_sku_to_speedo_ids(sku_info, &threshold);
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sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ);
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for (i = 0; i < GPU_PROCESS_CORNERS; i++)
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if (sku_info->gpu_speedo_value <
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gpu_process_speedos[threshold][i])
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break;
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sku_info->gpu_process_id = i;
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for (i = 0; i < CPU_PROCESS_CORNERS; i++)
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if (sku_info->cpu_speedo_value <
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cpu_process_speedos[threshold][i])
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break;
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sku_info->cpu_process_id = i;
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for (i = 0; i < SOC_PROCESS_CORNERS; i++)
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if (soc_speedo_0_value <
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soc_process_speedos[threshold][i])
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break;
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sku_info->soc_process_id = i;
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pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
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sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
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}
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