linux/drivers/clk/socfpga
Linus Torvalds 35655ceb31 Here's a collection of largely clk driver updates for the merge window. The
usual suspects are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and
 Rockchip, but it feels pretty light on commits. There's only one real commit to
 the framework core and that's to consolidate code. Otherwise the diffstat is
 dominated by many Qualcomm clk driver patches that modernize the driver for the
 proper way of speciying clk parents. That's shifting data around, which could
 subtly break things so I'll be on the lookout for fixes.
 
 New Drivers:
  - Proper clk driver for Mediatek MT7621 SoCs
  - Support for the clock controller on the new Rockchip rk3568
 
 Updates:
  - Simplify Zynq Kconfig dependencies
  - Use clk_hw pointers in socfpga driver
  - Cleanup parent data in qcom clk drivers
  - Some cleanups for rk3399 modularization
  - Fix reparenting of i.MX UART clocks by initializing only the ones
    associated to stdout
  - Correct the PCIE clocks for i.MX8MP and i.MX8MQ
  - Make i.MX LPCG and SCU clocks return on registering failure
  - Kernel doc fixes
  - Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N
  - Add timer (TMU) clocks on Renesas R-Car H3 ES1.0
  - Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on Renesas R-Car V3U
  - Sigma-delta modulation on Allwinner V3s audio PLL
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Here's a collection of largely clk driver updates. The usual suspects
  are here: i.MX, Qualcomm, Renesas, Allwinner, Samsung, and Rockchip,
  but it feels pretty light on commits.

  There's only one real commit to the framework core and that's to
  consolidate code. Otherwise the diffstat is dominated by many Qualcomm
  clk driver patches that modernize the driver for the proper way of
  speciying clk parents. That's shifting data around, which could subtly
  break things so I'll be on the lookout for fixes.

  New Drivers:
   - Proper clk driver for Mediatek MT7621 SoCs
   - Support for the clock controller on the new Rockchip rk3568

  Updates:
   - Simplify Zynq Kconfig dependencies
   - Use clk_hw pointers in socfpga driver
   - Cleanup parent data in qcom clk drivers
   - Some cleanups for rk3399 modularization
   - Fix reparenting of i.MX UART clocks by initializing only the ones
     associated to stdout
   - Correct the PCIE clocks for i.MX8MP and i.MX8MQ
   - Make i.MX LPCG and SCU clocks return on registering failure
   - Kernel doc fixes
   - Add DAB hardware accelerator clocks on Renesas R-Car E3 and M3-N
   - Add timer (TMU) clocks on Renesas R-Car H3 ES1.0
   - Add Timer (TMU & CMT) and thermal sensor (TSC) clocks on
     Renesas R-Car V3U
   - Sigma-delta modulation on Allwinner V3s audio PLL"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (82 commits)
  MAINTAINERS: add MT7621 CLOCK maintainer
  staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
  staging: mt7621-dts: make use of new 'mt7621-clk'
  clk: ralink: add clock driver for mt7621 SoC
  clk: uniphier: Fix potential infinite loop
  clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
  clk: qcom: gcc-sdm845: get rid of the test clock
  clk: qcom: convert SDM845 Global Clock Controller to parent_data
  dt-bindings: clock: separate SDM845 GCC clock bindings
  clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
  dt: bindings: add mt7621-sysc device tree binding documentation
  dt-bindings: clock: add dt binding header for mt7621 clocks
  clk: samsung: Remove redundant dev_err calls
  clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
  clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
  clk: zynqmp: Drop dependency on ARCH_ZYNQMP
  clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected
  clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
  ...
2021-04-28 17:13:56 -07:00
..
clk-agilex.c clk: socfpga: Fix code formatting 2021-03-30 19:31:26 -07:00
clk-gate-a10.c clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return 2021-04-07 16:29:31 -07:00
clk-gate-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-gate.c Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next 2021-04-27 16:34:28 -07:00
clk-periph-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph-s10.c clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-pll-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-pll-s10.c clk: socfpga: remove redundant initialization of variable div 2021-04-07 16:30:23 -07:00
clk-pll.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-s10.c clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
Kconfig clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
Makefile clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
stratix10-clk.h clk: socfpga: Convert to s10/agilex/n5x to use clk_hw 2021-03-30 19:26:26 -07:00