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313ce648b5
It adds support for extended length of read and write transactions. New CPLD logic allows double size of the read and write transactions length. This feature is verified through capability register, which is renamed from unclear LPF_REG to CPBLTY_REG. Two bits 5 and 6 of these register are used for length capability detection, while only 01 combination indicates support of extended transaction length. Others mean lack of such support. Signed-off-by: Michael Shych <michaelsh@mellanox.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> |
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| .. | ||
| algos | ||
| busses | ||
| muxes | ||
| i2c-boardinfo.c | ||
| i2c-core-acpi.c | ||
| i2c-core-base.c | ||
| i2c-core-of.c | ||
| i2c-core-slave.c | ||
| i2c-core-smbus.c | ||
| i2c-core.h | ||
| i2c-dev.c | ||
| i2c-mux.c | ||
| i2c-slave-eeprom.c | ||
| i2c-smbus.c | ||
| i2c-stub.c | ||
| Kconfig | ||
| Makefile | ||