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dd11376b9f
Split the drivers/scsi/ufs directory into 'core' and 'host' directories under the drivers/ufs/ directory. Move shared header files into the include/ufs/ directory. This separation makes it clear which header files UFS drivers are allowed to include (include/ufs/*.h) and which header files UFS drivers are not allowed to include (drivers/ufs/core/*.h). Update the MAINTAINERS file. Add myself as a UFS reviewer. Link: https://lore.kernel.org/r/20220511212552.655341-1-bvanassche@acm.org Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Avri Altman <avri.altman@wdc.com> Cc: Bean Huo <beanhuo@micron.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Keoseong Park <keosung.park@samsung.com> Tested-by: Bean Huo <beanhuo@micron.com> Tested-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Bean Huo <beanhuo@micron.com> Acked-by: Avri Altman <avri.altman@wdc.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
34 lines
730 B
C
34 lines
730 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*/
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#ifndef _UFSHCI_DWC_H
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#define _UFSHCI_DWC_H
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/* DWC HC UFSHCI specific Registers */
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enum dwc_specific_registers {
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DWC_UFS_REG_HCLKDIV = 0xFC,
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};
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/* Clock Divider Values: Hex equivalent of frequency in MHz */
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enum clk_div_values {
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DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
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DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
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DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
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};
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/* Selector Index */
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enum selector_index {
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SELIND_LN0_TX = 0x00,
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SELIND_LN1_TX = 0x01,
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SELIND_LN0_RX = 0x04,
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SELIND_LN1_RX = 0x05,
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};
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#endif /* End of Header */
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