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d5c4d1930c
The array we use will vary depending on whether or not we are to go to lower power or not. The default values (iniPcieSerdes) are a copy or what go into the registers through the INI files. Cc: Aeolus Yang <aeolus.yang@atheros.com> Cc: Madhan Jaganathan <madhan.jaganathan@atheros.com> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
339 lines
10 KiB
C
339 lines
10 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar9003_mac.h"
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#include "ar9003_2p0_initvals.h"
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#include "ar9003_2p2_initvals.h"
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/* General hardware code for the AR9003 hadware family */
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static bool ar9003_hw_macversion_supported(u32 macversion)
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{
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switch (macversion) {
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case AR_SREV_VERSION_9300:
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return true;
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default:
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break;
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}
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return false;
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}
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/* AR9003 2.0 */
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static void ar9003_2p0_hw_init_mode_regs(struct ath_hw *ah)
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{
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p0_mac_core,
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ARRAY_SIZE(ar9300_2p0_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p0_mac_postamble,
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ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p0_baseband_core,
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ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p0_baseband_postamble,
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ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p0_radio_core,
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ARRAY_SIZE(ar9300_2p0_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p0_radio_postamble,
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ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p0_soc_preamble,
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ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p0_soc_postamble,
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ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
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ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
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2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_clkreq_enable_L1_2p0,
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ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9300Modes_fast_clock_2p0,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
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3);
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}
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/* AR9003 2.2 */
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static void ar9003_2p2_hw_init_mode_regs(struct ath_hw *ah)
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{
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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ar9300_2p2_mac_core,
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ARRAY_SIZE(ar9300_2p2_mac_core), 2);
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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ar9300_2p2_mac_postamble,
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ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
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/* bb */
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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ar9300_2p2_baseband_core,
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ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
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INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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ar9300_2p2_baseband_postamble,
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ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
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/* radio */
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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ar9300_2p2_radio_core,
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ARRAY_SIZE(ar9300_2p2_radio_core), 2);
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INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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ar9300_2p2_radio_postamble,
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ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
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/* soc */
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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ar9300_2p2_soc_preamble,
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ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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ar9300_2p2_soc_postamble,
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ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
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/* rx/tx gain */
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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/* Load PCIE SERDES settings from INI */
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/* Awake Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
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2);
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/* Sleep Setting */
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INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
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ar9300PciePhy_clkreq_enable_L1_2p2,
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ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
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2);
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/* Fast clock modal settings */
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9300Modes_fast_clock_2p2,
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ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
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3);
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}
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/*
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* The AR9003 family uses a new INI format (pre, core, post
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* arrays per subsystem).
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*/
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static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
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{
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if (AR_SREV_9300_20(ah))
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ar9003_2p0_hw_init_mode_regs(ah);
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else
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ar9003_2p2_hw_init_mode_regs(ah);
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}
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static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
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{
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switch (ar9003_hw_get_tx_gain_idx(ah)) {
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case 0:
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default:
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
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5);
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break;
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case 1:
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_high_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
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5);
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break;
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case 2:
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p0,
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ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
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5);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9300Modes_low_ob_db_tx_gain_table_2p2,
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ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
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5);
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break;
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}
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}
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static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
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{
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switch (ar9003_hw_get_rx_gain_idx(ah)) {
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case 0:
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default:
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
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2);
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break;
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case 1:
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if (AR_SREV_9300_20(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p0,
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ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
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2);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9300Common_wo_xlna_rx_gain_table_2p2,
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ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
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2);
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break;
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}
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}
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/* set gain table pointers according to values read from the eeprom */
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static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
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{
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ar9003_tx_gain_table_apply(ah);
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ar9003_rx_gain_table_apply(ah);
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}
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/*
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* Helper for ASPM support.
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*
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* Disable PLL when in L0s as well as receiver clock when in L1.
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* This power saving option must be enabled through the SerDes.
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*
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* Programming the SerDes must go through the same 288 bit serial shift
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* register as the other analog registers. Hence the 9 writes.
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*/
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static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
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int restore,
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int power_off)
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{
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if (ah->is_pciexpress != true)
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return;
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/* Do not touch SerDes registers */
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if (ah->config.pcie_powersave_enable == 2)
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return;
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/* Nothing to do on restore for 11N */
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if (!restore) {
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/* set bit 19 to allow forcing of pcie core into L1 state */
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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/* Several PCIe massages to ensure proper behaviour */
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if (ah->config.pcie_waen)
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REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
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else
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REG_WRITE(ah, AR_WA, ah->WARegVal);
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}
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/*
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* Configire PCIE after Ini init. SERDES values now come from ini file
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* This enables PCIe low power mode.
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*/
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if (ah->config.pcieSerDesWrite) {
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unsigned int i;
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struct ar5416IniArray *array;
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array = power_off ? &ah->iniPcieSerdes :
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&ah->iniPcieSerdesLowPower;
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for (i = 0; i < array->ia_rows; i++) {
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REG_WRITE(ah,
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INI_RA(array, i, 0),
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INI_RA(array, i, 1));
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}
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}
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}
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/* Sets up the AR9003 hardware familiy callbacks */
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void ar9003_hw_attach_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
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priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
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priv_ops->macversion_supported = ar9003_hw_macversion_supported;
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ops->config_pci_powersave = ar9003_hw_configpcipowersave;
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ar9003_hw_attach_phy_ops(ah);
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ar9003_hw_attach_calib_ops(ah);
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ar9003_hw_attach_mac_ops(ah);
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ath9k_hw_attach_ani_ops_new(ah);
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}
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