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41a5e1cf1f
To avoid code duplication between the old tpm_tis and the new and future native tcg tis driver(ie: spi, i2c...), the tpm_tis driver was reworked, so that all common logic is extracted and can be reused from all drivers. The core methods can also be used from other TIS like drivers. itpm workaround is now managed with a specific tis flag TPM_TIS_ITPM_POSSIBLE. This commit is based on the initial work by Peter Huewe. Signed-off-by: Peter Huewe <peter.huewe@infineon.com> Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Tested-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Tested-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
157 lines
4.3 KiB
C
157 lines
4.3 KiB
C
/*
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* Copyright (C) 2005, 2006 IBM Corporation
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* Copyright (C) 2014, 2015 Intel Corporation
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*
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* Authors:
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* Leendert van Doorn <leendert@watson.ibm.com>
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* Kylene Hall <kjhall@us.ibm.com>
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*
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* Maintained by: <tpmdd-devel@lists.sourceforge.net>
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*
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* Device driver for TCG/TCPA TPM (trusted platform module).
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* Specifications at www.trustedcomputinggroup.org
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*
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* This device driver implements the TPM interface as defined in
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* the TCG TPM Interface Spec version 1.2, revision 1.0.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2 of the
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* License.
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*/
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#ifndef __TPM_TIS_CORE_H__
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#define __TPM_TIS_CORE_H__
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#include "tpm.h"
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enum tis_access {
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TPM_ACCESS_VALID = 0x80,
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TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
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TPM_ACCESS_REQUEST_PENDING = 0x04,
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TPM_ACCESS_REQUEST_USE = 0x02,
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};
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enum tis_status {
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TPM_STS_VALID = 0x80,
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TPM_STS_COMMAND_READY = 0x40,
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TPM_STS_GO = 0x20,
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TPM_STS_DATA_AVAIL = 0x10,
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TPM_STS_DATA_EXPECT = 0x08,
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};
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enum tis_int_flags {
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TPM_GLOBAL_INT_ENABLE = 0x80000000,
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TPM_INTF_BURST_COUNT_STATIC = 0x100,
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TPM_INTF_CMD_READY_INT = 0x080,
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TPM_INTF_INT_EDGE_FALLING = 0x040,
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TPM_INTF_INT_EDGE_RISING = 0x020,
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TPM_INTF_INT_LEVEL_LOW = 0x010,
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TPM_INTF_INT_LEVEL_HIGH = 0x008,
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TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
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TPM_INTF_STS_VALID_INT = 0x002,
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TPM_INTF_DATA_AVAIL_INT = 0x001,
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};
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enum tis_defaults {
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TIS_MEM_LEN = 0x5000,
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TIS_SHORT_TIMEOUT = 750, /* ms */
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TIS_LONG_TIMEOUT = 2000, /* 2 sec */
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};
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/* Some timeout values are needed before it is known whether the chip is
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* TPM 1.0 or TPM 2.0.
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*/
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#define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
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#define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
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#define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
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#define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
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#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
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#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
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#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
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#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
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#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
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#define TPM_STS(l) (0x0018 | ((l) << 12))
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#define TPM_STS3(l) (0x001b | ((l) << 12))
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#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
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#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
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#define TPM_RID(l) (0x0F04 | ((l) << 12))
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enum tpm_tis_flags {
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TPM_TIS_ITPM_POSSIBLE = BIT(0),
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};
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struct tpm_tis_data {
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u16 manufacturer_id;
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int locality;
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int irq;
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bool irq_tested;
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unsigned int flags;
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wait_queue_head_t int_queue;
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wait_queue_head_t read_queue;
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const struct tpm_tis_phy_ops *phy_ops;
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};
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struct tpm_tis_phy_ops {
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int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *result);
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int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *value);
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int (*read16)(struct tpm_tis_data *data, u32 addr, u16 *result);
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int (*read32)(struct tpm_tis_data *data, u32 addr, u32 *result);
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int (*write32)(struct tpm_tis_data *data, u32 addr, u32 src);
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};
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static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *result)
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{
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return data->phy_ops->read_bytes(data, addr, len, result);
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}
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static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
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{
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return data->phy_ops->read_bytes(data, addr, 1, result);
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}
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static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
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u16 *result)
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{
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return data->phy_ops->read16(data, addr, result);
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}
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static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
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u32 *result)
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{
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return data->phy_ops->read32(data, addr, result);
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}
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static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *value)
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{
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return data->phy_ops->write_bytes(data, addr, len, value);
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}
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static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
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{
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return data->phy_ops->write_bytes(data, addr, 1, &value);
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}
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static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
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u32 value)
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{
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return data->phy_ops->write32(data, addr, value);
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}
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void tpm_tis_remove(struct tpm_chip *chip);
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int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
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const struct tpm_tis_phy_ops *phy_ops,
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acpi_handle acpi_dev_handle);
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#ifdef CONFIG_PM_SLEEP
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int tpm_tis_resume(struct device *dev);
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#endif
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#endif
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