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Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
152 lines
3 KiB
C
152 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "clk.h"
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/**
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* struct clk_pfd - IMX PFD clock
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* @clk_hw: clock source
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* @reg: PFD register address
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* @idx: the index of PFD encoded in the register
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*
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* PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd
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* data encoded, and member idx is used to specify the one. And each
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* register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
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*/
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struct clk_pfd {
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struct clk_hw hw;
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void __iomem *reg;
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u8 idx;
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};
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#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
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#define SET 0x4
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#define CLR 0x8
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#define OTG 0xc
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static int clk_pfd_enable(struct clk_hw *hw)
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{
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struct clk_pfd *pfd = to_clk_pfd(hw);
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writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
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return 0;
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}
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static void clk_pfd_disable(struct clk_hw *hw)
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{
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struct clk_pfd *pfd = to_clk_pfd(hw);
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writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
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}
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static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pfd *pfd = to_clk_pfd(hw);
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u64 tmp = parent_rate;
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u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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u64 tmp = *prate;
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u8 frac;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 12)
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frac = 12;
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else if (frac > 35)
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frac = 35;
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tmp = *prate;
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tmp *= 18;
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do_div(tmp, frac);
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return tmp;
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}
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static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pfd *pfd = to_clk_pfd(hw);
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u64 tmp = parent_rate;
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u8 frac;
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tmp = tmp * 18 + rate / 2;
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do_div(tmp, rate);
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frac = tmp;
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if (frac < 12)
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frac = 12;
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else if (frac > 35)
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frac = 35;
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writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
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writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
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return 0;
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}
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static int clk_pfd_is_enabled(struct clk_hw *hw)
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{
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struct clk_pfd *pfd = to_clk_pfd(hw);
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if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
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return 0;
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return 1;
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}
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static const struct clk_ops clk_pfd_ops = {
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.enable = clk_pfd_enable,
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.disable = clk_pfd_disable,
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.recalc_rate = clk_pfd_recalc_rate,
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.round_rate = clk_pfd_round_rate,
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.set_rate = clk_pfd_set_rate,
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.is_enabled = clk_pfd_is_enabled,
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};
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx)
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{
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struct clk_pfd *pfd;
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struct clk *clk;
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struct clk_init_data init;
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pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
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if (!pfd)
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return ERR_PTR(-ENOMEM);
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pfd->reg = reg;
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pfd->idx = idx;
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init.name = name;
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init.ops = &clk_pfd_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pfd->hw.init = &init;
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clk = clk_register(NULL, &pfd->hw);
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if (IS_ERR(clk))
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kfree(pfd);
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return clk;
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}
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