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https://github.com/torvalds/linux
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2a0f8918fc
Doing this like the DDX seems like the most sure fire way to avoid having to reinvent it slowly and painfully. At the moment we keep getting things wrong with aper vs vram, so we know the DDX does it right. booted on PCI r100, PCIE rv370, IGP rs400. Signed-off-by: Dave Airlie <airlied@redhat.com>
233 lines
6.3 KiB
C
233 lines
6.3 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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/* r520,rv530,rv560,rv570,r580 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int rv370_pcie_gart_enable(struct radeon_device *rdev);
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void rv370_pcie_gart_disable(struct radeon_device *rdev);
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void r420_pipes_init(struct radeon_device *rdev);
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void rs600_mc_disable_clients(struct radeon_device *rdev);
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void rs600_disable_vga(struct radeon_device *rdev);
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int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
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int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
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/* This files gather functions specifics to:
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* r520,rv530,rv560,rv570,r580
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void r520_gpu_init(struct radeon_device *rdev);
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int r520_mc_wait_for_idle(struct radeon_device *rdev);
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/*
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* MC
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*/
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int r520_mc_init(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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if (rv515_debugfs_pipes_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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if (rv515_debugfs_ga_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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r520_gpu_init(rdev);
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rv370_pcie_gart_disable(rdev);
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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printk(KERN_WARNING "[drm] Disabling AGP\n");
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rdev->flags &= ~RADEON_IS_AGP;
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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rs600_mc_disable_clients(rdev);
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if (r520_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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/* Write VRAM size in case we are limiting it */
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WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
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tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
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tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
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tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32_MC(R520_MC_FB_LOCATION, tmp);
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WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
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WREG32(0x310, rdev->mc.vram_location);
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if (rdev->flags & RADEON_IS_AGP) {
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
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tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
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WREG32_MC(R520_MC_AGP_LOCATION, tmp);
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WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
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WREG32_MC(R520_MC_AGP_BASE_2, 0);
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} else {
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WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
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WREG32_MC(R520_MC_AGP_BASE, 0);
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WREG32_MC(R520_MC_AGP_BASE_2, 0);
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}
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return 0;
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}
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void r520_mc_fini(struct radeon_device *rdev)
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{
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rv370_pcie_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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radeon_gart_fini(rdev);
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}
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/*
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* Global GPU functions
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*/
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void r520_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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int r520_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(R520_MC_STATUS);
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if (tmp & R520_MC_STATUS_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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void r520_gpu_init(struct radeon_device *rdev)
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{
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unsigned pipe_select_current, gb_pipe_select, tmp;
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r100_hdp_reset(rdev);
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rs600_disable_vga(rdev);
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/*
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* DST_PIPE_CONFIG 0x170C
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* GB_TILE_CONFIG 0x4018
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* GB_FIFO_SIZE 0x4024
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* GB_PIPE_SELECT 0x402C
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* GB_PIPE_SELECT2 0x4124
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* Z_PIPE_SHIFT 0
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* Z_PIPE_MASK 0x000000003
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* GB_FIFO_SIZE2 0x4128
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* SC_SFIFO_SIZE_SHIFT 0
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* SC_SFIFO_SIZE_MASK 0x000000003
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* SC_MFIFO_SIZE_SHIFT 2
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* SC_MFIFO_SIZE_MASK 0x00000000C
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* FG_SFIFO_SIZE_SHIFT 4
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* FG_SFIFO_SIZE_MASK 0x000000030
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* ZB_MFIFO_SIZE_SHIFT 6
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* ZB_MFIFO_SIZE_MASK 0x0000000C0
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* GA_ENHANCE 0x4274
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* SU_REG_DEST 0x42C8
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*/
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/* workaround for RV530 */
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if (rdev->family == CHIP_RV530) {
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WREG32(0x4124, 1);
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WREG32(0x4128, 0xFF);
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}
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r420_pipes_init(rdev);
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gb_pipe_select = RREG32(0x402C);
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tmp = RREG32(0x170C);
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pipe_select_current = (tmp >> 2) & 3;
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tmp = (1 << pipe_select_current) |
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(((gb_pipe_select >> 8) & 0xF) << 4);
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WREG32_PLL(0x000D, tmp);
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if (r520_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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/*
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* VRAM info
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*/
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static void r520_vram_get_type(struct radeon_device *rdev)
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{
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uint32_t tmp;
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rdev->mc.vram_width = 128;
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rdev->mc.vram_is_ddr = true;
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tmp = RREG32_MC(R520_MC_CNTL0);
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switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
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case 0:
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rdev->mc.vram_width = 32;
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break;
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case 1:
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rdev->mc.vram_width = 64;
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break;
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case 2:
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rdev->mc.vram_width = 128;
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break;
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case 3:
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rdev->mc.vram_width = 256;
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break;
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default:
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rdev->mc.vram_width = 128;
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break;
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}
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if (tmp & R520_MC_CHANNEL_SIZE)
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rdev->mc.vram_width *= 2;
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}
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void r520_vram_info(struct radeon_device *rdev)
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{
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r520_vram_get_type(rdev);
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r100_vram_init_sizes(rdev);
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}
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