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https://github.com/torvalds/linux
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ea3cc330ac
This is an attempt at cleaning up a bit the way we handle execute permission on powerpc. _PAGE_HWEXEC is gone, _PAGE_EXEC is now only defined by CPUs that can do something with it, and the myriad of #ifdef's in the I$/D$ coherency code is reduced to 2 cases that hopefully should cover everything. The logic on BookE is a little bit different than what it was though not by much. Since now, _PAGE_EXEC will be set by the generic code for executable pages, we need to filter out if they are unclean and recover it. However, I don't expect the code to be more bloated than it already was in that area due to that change. I could boast that this brings proper enforcing of per-page execute permissions to all BookE and 40x but in fact, we've had that now for some time as a side effect of my previous rework in that area (and I didn't even know it :-) We would only enable execute permission if the page was cache clean and we would only cache clean it if we took and exec fault. Since we now enforce that the later only work if VM_EXEC is part of the VMA flags, we de-fact already enforce per-page execute permissions... Unless I missed something Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
147 lines
4 KiB
C
147 lines
4 KiB
C
/*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/stddef.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <asm/pgalloc.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/uaccess.h>
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#include <asm/smp.h>
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#include <asm/bootx.h>
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#include <asm/machdep.h>
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#include <asm/setup.h>
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#include "mmu_decl.h"
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extern int __map_without_ltlbs;
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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/*
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* The Zone Protection Register (ZPR) defines how protection will
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* be applied to every page which is a member of a given zone. At
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* present, we utilize only two of the 4xx's zones.
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* The zone index bits (of ZSEL) in the PTE are used for software
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* indicators, except the LSB. For user access, zone 1 is used,
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* for kernel access, zone 0 is used. We set all but zone 1
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* to zero, allowing only kernel access as indicated in the PTE.
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* For zone 1, we set a 01 binary (a value of 10 will not work)
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* to allow user access as indicated in the PTE. This also allows
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* kernel access as indicated in the PTE.
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*/
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mtspr(SPRN_ZPR, 0x10000000);
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flush_instruction_cache();
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/*
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* Set up the real-mode cache parameters for the exception vector
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* handlers (which are run in real-mode).
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*/
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mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
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/*
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* Cache instruction and data space where the exception
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* vectors and the kernel live in real-mode.
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*/
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mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */
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mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */
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}
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#define LARGE_PAGE_SIZE_16M (1<<24)
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#define LARGE_PAGE_SIZE_4M (1<<22)
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unsigned long __init mmu_mapin_ram(void)
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{
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unsigned long v, s, mapped;
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phys_addr_t p;
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v = KERNELBASE;
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p = 0;
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s = total_lowmem;
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if (__map_without_ltlbs)
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return 0;
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while (s >= LARGE_PAGE_SIZE_16M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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pmd_val(*pmdp++) = val;
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pmd_val(*pmdp++) = val;
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pmd_val(*pmdp++) = val;
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pmd_val(*pmdp++) = val;
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v += LARGE_PAGE_SIZE_16M;
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p += LARGE_PAGE_SIZE_16M;
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s -= LARGE_PAGE_SIZE_16M;
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}
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while (s >= LARGE_PAGE_SIZE_4M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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pmd_val(*pmdp) = val;
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v += LARGE_PAGE_SIZE_4M;
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p += LARGE_PAGE_SIZE_4M;
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s -= LARGE_PAGE_SIZE_4M;
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}
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mapped = total_lowmem - s;
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/* If the size of RAM is not an exact power of two, we may not
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* have covered RAM in its entirety with 16 and 4 MiB
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* pages. Consequently, restrict the top end of RAM currently
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* allocable so that calls to the LMB to allocate PTEs for "tail"
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* coverage with normal-sized pages (or other reasons) do not
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* attempt to allocate outside the allowed range.
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*/
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__initial_memory_limit_addr = memstart_addr + mapped;
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return mapped;
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}
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