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61f4399c74
Implement CPU clock control for Exynos850 SoC. It follows the same procedure which is already implemented for other SoCs in clk-cpu.c: 1. Set the correct rate for the alternate parent (if needed) before switching to use it as the CPU clock 2. Switch to the alternate parent, so the CPU continues to get clocked while the PLL is being re-configured 3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc) 4. Re-configure the PLL for the new CPU clock rate. It's done automatically, as the CPU clock rate change propagates to the PLL clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in exynos_register_cpu_clock() 5. Once the PLL is locked, set it back as the CPU clock source 6. Set alternate parent clock rate back to max speed As in already existing clk-cpu.c code, the divider and mux clocks are configured in a low-level fashion (using direct register access instead of CCF API), to avoid affecting how DIV and MUX clock flags are declared in the actual clock driver (clk-exynos850.c). No functional change. This patch adds support for Exynos850 CPU clock, but doesn't enable it per se. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-13-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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*
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* Common Clock Framework support for all PLL's in Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_CPU_H
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#define __SAMSUNG_CLK_CPU_H
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/* The CPU clock registers have DIV1 configuration register */
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#define CLK_CPU_HAS_DIV1 BIT(0)
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/* When ALT parent is active, debug clocks need safe divider values */
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#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1)
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/**
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* enum exynos_cpuclk_layout - CPU clock registers layout compatibility
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* @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout
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* @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout
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* @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout
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* @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout
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*/
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enum exynos_cpuclk_layout {
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CPUCLK_LAYOUT_E4210,
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CPUCLK_LAYOUT_E5433,
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CPUCLK_LAYOUT_E850_CL0,
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CPUCLK_LAYOUT_E850_CL1,
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};
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/**
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* struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
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* @prate: frequency of the primary parent clock (in KHz)
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* @div0: value to be programmed in the div_cpu0 register
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* @div1: value to be programmed in the div_cpu1 register
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*
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* This structure holds the divider configuration data for dividers in the CPU
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* clock domain. The parent frequency at which these divider values are valid is
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* specified in @prate. The @prate is the frequency of the primary parent clock.
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* For CPU clock domains that do not have a DIV1 register, the @div1 member
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* value is not used.
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*/
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struct exynos_cpuclk_cfg_data {
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unsigned long prate;
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unsigned long div0;
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unsigned long div1;
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};
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#endif /* __SAMSUNG_CLK_CPU_H */
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