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e787c9c55e
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
39 lines
1.7 KiB
C
39 lines
1.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
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* Author: Yu Tu <yu.tu@amlogic.com>
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*/
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#ifndef __MESON_S4_PLL_H__
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#define __MESON_S4_PLL_H__
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#define ANACTRL_FIXPLL_CTRL0 0x040
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#define ANACTRL_FIXPLL_CTRL1 0x044
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#define ANACTRL_FIXPLL_CTRL3 0x04c
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#define ANACTRL_GP0PLL_CTRL0 0x080
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#define ANACTRL_GP0PLL_CTRL1 0x084
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#define ANACTRL_GP0PLL_CTRL2 0x088
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#define ANACTRL_GP0PLL_CTRL3 0x08c
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#define ANACTRL_GP0PLL_CTRL4 0x090
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#define ANACTRL_GP0PLL_CTRL5 0x094
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#define ANACTRL_GP0PLL_CTRL6 0x098
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#define ANACTRL_HIFIPLL_CTRL0 0x100
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#define ANACTRL_HIFIPLL_CTRL1 0x104
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#define ANACTRL_HIFIPLL_CTRL2 0x108
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#define ANACTRL_HIFIPLL_CTRL3 0x10c
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#define ANACTRL_HIFIPLL_CTRL4 0x110
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#define ANACTRL_HIFIPLL_CTRL5 0x114
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#define ANACTRL_HIFIPLL_CTRL6 0x118
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#define ANACTRL_MPLL_CTRL0 0x180
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#define ANACTRL_MPLL_CTRL1 0x184
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#define ANACTRL_MPLL_CTRL2 0x188
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#define ANACTRL_MPLL_CTRL3 0x18c
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#define ANACTRL_MPLL_CTRL4 0x190
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#define ANACTRL_MPLL_CTRL5 0x194
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#define ANACTRL_MPLL_CTRL6 0x198
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#define ANACTRL_MPLL_CTRL7 0x19c
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#define ANACTRL_MPLL_CTRL8 0x1a0
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#define ANACTRL_HDMIPLL_CTRL0 0x1c0
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#endif /* __MESON_S4_PLL_H__ */
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