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a96cbb146a
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs vdec0_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x4,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs vdec1_cg_regs = {
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.set_ofs = 0x200,
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.clr_ofs = 0x204,
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.sta_ofs = 0x200,
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};
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static const struct mtk_gate_regs vdec2_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xc,
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.sta_ofs = 0x8,
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};
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#define GATE_VDEC0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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#define GATE_VDEC1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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#define GATE_VDEC2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
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static const struct mtk_gate vdec_clks[] = {
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/* VDEC0 */
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GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
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GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
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/* VDEC1 */
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GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
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GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
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/* VDEC2 */
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GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
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};
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static const struct mtk_gate vdec_soc_clks[] = {
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/* VDEC_SOC0 */
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GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
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GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
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/* VDEC_SOC1 */
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GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
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GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
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/* VDEC_SOC2 */
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GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
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};
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static const struct mtk_clk_desc vdec_desc = {
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.clks = vdec_clks,
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.num_clks = ARRAY_SIZE(vdec_clks),
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};
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static const struct mtk_clk_desc vdec_soc_desc = {
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.clks = vdec_soc_clks,
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.num_clks = ARRAY_SIZE(vdec_soc_clks),
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};
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static const struct of_device_id of_match_clk_mt8192_vdec[] = {
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{
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.compatible = "mediatek,mt8192-vdecsys",
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.data = &vdec_desc,
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}, {
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.compatible = "mediatek,mt8192-vdecsys_soc",
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.data = &vdec_soc_desc,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec);
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static struct platform_driver clk_mt8192_vdec_drv = {
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.probe = mtk_clk_simple_probe,
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.remove_new = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8192-vdec",
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.of_match_table = of_match_clk_mt8192_vdec,
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},
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};
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module_platform_driver(clk_mt8192_vdec_drv);
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MODULE_LICENSE("GPL");
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