Lubomir Rintel 0ea8cbc15d clk: mmp2: separate LCDC peripheral clk form the display clock ... These are in fact two clocks, they shouldn't be exposed as one. One is required for accessing LCD controller registers (peripheral clock), while other (AXI clock) can be optionally used as a pixel clock source for the panel. LCDC can alternatively use different clocks than the Display 1 AXI clock for generating the pixel clock: the second AXI clock (fixed in this commit too), the HDMI PLL, or the AXI bus clock. They should really be controlled independently. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-02-21 13:52:02 -08:00
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clk-apbc.c
clk-apmu.c
clk-frac.c
clk-gate.c
clk-mix.c
clk-mmp2.c
clk-of-mmp2.c	clk: mmp2: separate LCDC peripheral clk form the display clock	2019-02-21 13:52:02 -08:00
clk-of-pxa168.c
clk-of-pxa910.c
clk-of-pxa1928.c
clk-pxa168.c
clk-pxa910.c
clk.c
clk.h
Makefile
reset.c
reset.h