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bd6f27458b
In the ISI driver it reads the config register to get original value, then set the correct FRATE_DIV and YCC_SWAP_MODE directly. This will cause some bits overlap. So we need to clear these bits first, then set correct value. This patch fix it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
123 lines
3.6 KiB
C
123 lines
3.6 KiB
C
/*
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* Register definitions for the Atmel Image Sensor Interface.
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*
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* Copyright (C) 2011 Atmel Corporation
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* Josh Wu, <josh.wu@atmel.com>
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*
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* Based on previous work by Lars Haring, <lars.haring@atmel.com>
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* and Sedji Gaouaou
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ATMEL_ISI_H__
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#define __ATMEL_ISI_H__
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#include <linux/types.h>
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/* ISI_V2 register offsets */
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#define ISI_CFG1 0x0000
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#define ISI_CFG2 0x0004
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#define ISI_PSIZE 0x0008
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#define ISI_PDECF 0x000c
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#define ISI_Y2R_SET0 0x0010
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#define ISI_Y2R_SET1 0x0014
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#define ISI_R2Y_SET0 0x0018
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#define ISI_R2Y_SET1 0x001C
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#define ISI_R2Y_SET2 0x0020
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#define ISI_CTRL 0x0024
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#define ISI_STATUS 0x0028
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#define ISI_INTEN 0x002C
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#define ISI_INTDIS 0x0030
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#define ISI_INTMASK 0x0034
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#define ISI_DMA_CHER 0x0038
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#define ISI_DMA_CHDR 0x003C
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#define ISI_DMA_CHSR 0x0040
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#define ISI_DMA_P_ADDR 0x0044
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#define ISI_DMA_P_CTRL 0x0048
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#define ISI_DMA_P_DSCR 0x004C
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#define ISI_DMA_C_ADDR 0x0050
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#define ISI_DMA_C_CTRL 0x0054
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#define ISI_DMA_C_DSCR 0x0058
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/* Bitfields in CFG1 */
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#define ISI_CFG1_HSYNC_POL_ACTIVE_LOW (1 << 2)
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#define ISI_CFG1_VSYNC_POL_ACTIVE_LOW (1 << 3)
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#define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING (1 << 4)
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#define ISI_CFG1_EMB_SYNC (1 << 6)
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#define ISI_CFG1_CRC_SYNC (1 << 7)
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/* Constants for FRATE(ISI_V2) */
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#define ISI_CFG1_FRATE_CAPTURE_ALL (0 << 8)
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#define ISI_CFG1_FRATE_DIV_2 (1 << 8)
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#define ISI_CFG1_FRATE_DIV_3 (2 << 8)
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#define ISI_CFG1_FRATE_DIV_4 (3 << 8)
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#define ISI_CFG1_FRATE_DIV_5 (4 << 8)
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#define ISI_CFG1_FRATE_DIV_6 (5 << 8)
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#define ISI_CFG1_FRATE_DIV_7 (6 << 8)
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#define ISI_CFG1_FRATE_DIV_8 (7 << 8)
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#define ISI_CFG1_FRATE_DIV_MASK (7 << 8)
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#define ISI_CFG1_DISCR (1 << 11)
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#define ISI_CFG1_FULL_MODE (1 << 12)
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/* Bitfields in CFG2 */
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#define ISI_CFG2_GRAYSCALE (1 << 13)
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/* Constants for YCC_SWAP(ISI_V2) */
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#define ISI_CFG2_YCC_SWAP_DEFAULT (0 << 28)
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#define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28)
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#define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28)
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#define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28)
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#define ISI_CFG2_YCC_SWAP_MODE_MASK (3 << 28)
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#define ISI_CFG2_IM_VSIZE_OFFSET 0
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#define ISI_CFG2_IM_HSIZE_OFFSET 16
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#define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)
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#define ISI_CFG2_IM_HSIZE_MASK (0x7FF << ISI_CFG2_IM_HSIZE_OFFSET)
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/* Bitfields in CTRL */
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/* Also using in SR(ISI_V2) */
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#define ISI_CTRL_EN (1 << 0)
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#define ISI_CTRL_CDC (1 << 8)
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/* Also using in SR/IER/IDR/IMR(ISI_V2) */
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#define ISI_CTRL_DIS (1 << 1)
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#define ISI_CTRL_SRST (1 << 2)
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/* Bitfields in SR */
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#define ISI_SR_SIP (1 << 19)
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/* Also using in SR/IER/IDR/IMR */
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#define ISI_SR_VSYNC (1 << 10)
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#define ISI_SR_PXFR_DONE (1 << 16)
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#define ISI_SR_CXFR_DONE (1 << 17)
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#define ISI_SR_P_OVR (1 << 24)
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#define ISI_SR_C_OVR (1 << 25)
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#define ISI_SR_CRC_ERR (1 << 26)
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#define ISI_SR_FR_OVR (1 << 27)
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/* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */
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#define ISI_DMA_CTRL_FETCH (1 << 0)
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#define ISI_DMA_CTRL_WB (1 << 1)
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#define ISI_DMA_CTRL_IEN (1 << 2)
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#define ISI_DMA_CTRL_DONE (1 << 3)
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/* Bitfields in DMA_CHSR/CHER/CHDR */
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#define ISI_DMA_CHSR_P_CH (1 << 0)
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#define ISI_DMA_CHSR_C_CH (1 << 1)
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/* Definition for isi_platform_data */
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#define ISI_DATAWIDTH_8 0x01
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#define ISI_DATAWIDTH_10 0x02
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struct isi_platform_data {
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u8 has_emb_sync;
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u8 emb_crc_sync;
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u8 hsync_act_low;
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u8 vsync_act_low;
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u8 pclk_act_falling;
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u8 full_mode;
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u32 data_width_flags;
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/* Using for ISI_CFG1 */
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u32 frate;
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/* Using for ISI_MCK */
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u32 mck_hz;
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};
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#endif /* __ATMEL_ISI_H__ */
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