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7f47d8cc03
For debugging low level code interacting with the CPU it is often useful to trace the MSR read/writes. This gives a concise summary of PMU and other operations. perf has an ad-hoc way to do this using trace_printk, but it's somewhat limited (and also now spews ugly boot messages when enabled) Instead define real trace points for all MSR accesses. This adds three new trace points: read_msr and write_msr and rdpmc. They also report if the access faulted (if *_safe is used) This allows filtering and triggering on specific MSR values, which allows various more advanced debugging techniques. All the values are well defined in the CPU documentation. The trace can be post processed with Documentation/trace/postprocess/decode_msr.py to add symbolic MSR names to the trace. I only added it to native MSR accesses in C, not paravirtualized or in entry*.S (which is not too interesting) Originally the patch kit moved the MSRs out of line. This uses an alternative approach recommended by Steven Rostedt of only moving the trace calls out of line, but open coding the access to the jump label. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Steven Rostedt <rostedt@goodmis.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1449018060-1742-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
137 lines
2.2 KiB
C
137 lines
2.2 KiB
C
#include <linux/module.h>
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#include <linux/preempt.h>
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#include <asm/msr.h>
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#define CREATE_TRACE_POINTS
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#include <asm/msr-trace.h>
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struct msr *msrs_alloc(void)
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{
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struct msr *msrs = NULL;
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msrs = alloc_percpu(struct msr);
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if (!msrs) {
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pr_warn("%s: error allocating msrs\n", __func__);
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return NULL;
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}
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return msrs;
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}
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EXPORT_SYMBOL(msrs_alloc);
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void msrs_free(struct msr *msrs)
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{
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free_percpu(msrs);
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}
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EXPORT_SYMBOL(msrs_free);
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/**
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* Read an MSR with error handling
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*
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* @msr: MSR to read
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* @m: value to read into
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*
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* It returns read data only on success, otherwise it doesn't change the output
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* argument @m.
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*
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*/
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int msr_read(u32 msr, struct msr *m)
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{
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int err;
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u64 val;
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err = rdmsrl_safe(msr, &val);
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if (!err)
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m->q = val;
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return err;
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}
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/**
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* Write an MSR with error handling
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*
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* @msr: MSR to write
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* @m: value to write
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*/
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int msr_write(u32 msr, struct msr *m)
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{
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return wrmsrl_safe(msr, m->q);
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}
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static inline int __flip_bit(u32 msr, u8 bit, bool set)
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{
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struct msr m, m1;
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int err = -EINVAL;
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if (bit > 63)
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return err;
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err = msr_read(msr, &m);
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if (err)
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return err;
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m1 = m;
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if (set)
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m1.q |= BIT_64(bit);
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else
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m1.q &= ~BIT_64(bit);
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if (m1.q == m.q)
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return 0;
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err = msr_write(msr, &m1);
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if (err)
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return err;
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return 1;
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}
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/**
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* Set @bit in a MSR @msr.
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*
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* Retval:
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* < 0: An error was encountered.
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* = 0: Bit was already set.
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* > 0: Hardware accepted the MSR write.
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*/
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int msr_set_bit(u32 msr, u8 bit)
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{
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return __flip_bit(msr, bit, true);
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}
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/**
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* Clear @bit in a MSR @msr.
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*
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* Retval:
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* < 0: An error was encountered.
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* = 0: Bit was already cleared.
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* > 0: Hardware accepted the MSR write.
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*/
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int msr_clear_bit(u32 msr, u8 bit)
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{
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return __flip_bit(msr, bit, false);
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}
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#ifdef CONFIG_TRACEPOINTS
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void do_trace_write_msr(unsigned msr, u64 val, int failed)
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{
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trace_write_msr(msr, val, failed);
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}
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EXPORT_SYMBOL(do_trace_write_msr);
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EXPORT_TRACEPOINT_SYMBOL(write_msr);
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void do_trace_read_msr(unsigned msr, u64 val, int failed)
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{
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trace_read_msr(msr, val, failed);
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}
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EXPORT_SYMBOL(do_trace_read_msr);
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EXPORT_TRACEPOINT_SYMBOL(read_msr);
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void do_trace_rdpmc(unsigned counter, u64 val, int failed)
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{
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trace_rdpmc(counter, val, failed);
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}
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EXPORT_SYMBOL(do_trace_rdpmc);
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EXPORT_TRACEPOINT_SYMBOL(rdpmc);
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#endif
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