mirror of
https://github.com/torvalds/linux
synced 2024-10-17 00:39:37 +00:00
22ee670a8a
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
653 lines
19 KiB
C
653 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "pinctrl-msm.h"
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static const struct pinctrl_pin_desc ipq8064_pins[] = {
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PINCTRL_PIN(0, "GPIO_0"),
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PINCTRL_PIN(1, "GPIO_1"),
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PINCTRL_PIN(2, "GPIO_2"),
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PINCTRL_PIN(3, "GPIO_3"),
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PINCTRL_PIN(4, "GPIO_4"),
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PINCTRL_PIN(5, "GPIO_5"),
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PINCTRL_PIN(6, "GPIO_6"),
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PINCTRL_PIN(7, "GPIO_7"),
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PINCTRL_PIN(8, "GPIO_8"),
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PINCTRL_PIN(9, "GPIO_9"),
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PINCTRL_PIN(10, "GPIO_10"),
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PINCTRL_PIN(11, "GPIO_11"),
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PINCTRL_PIN(12, "GPIO_12"),
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PINCTRL_PIN(13, "GPIO_13"),
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PINCTRL_PIN(14, "GPIO_14"),
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PINCTRL_PIN(15, "GPIO_15"),
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PINCTRL_PIN(16, "GPIO_16"),
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PINCTRL_PIN(17, "GPIO_17"),
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PINCTRL_PIN(18, "GPIO_18"),
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PINCTRL_PIN(19, "GPIO_19"),
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PINCTRL_PIN(20, "GPIO_20"),
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PINCTRL_PIN(21, "GPIO_21"),
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PINCTRL_PIN(22, "GPIO_22"),
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PINCTRL_PIN(23, "GPIO_23"),
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PINCTRL_PIN(24, "GPIO_24"),
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PINCTRL_PIN(25, "GPIO_25"),
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PINCTRL_PIN(26, "GPIO_26"),
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PINCTRL_PIN(27, "GPIO_27"),
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PINCTRL_PIN(28, "GPIO_28"),
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PINCTRL_PIN(29, "GPIO_29"),
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PINCTRL_PIN(30, "GPIO_30"),
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PINCTRL_PIN(31, "GPIO_31"),
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PINCTRL_PIN(32, "GPIO_32"),
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PINCTRL_PIN(33, "GPIO_33"),
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PINCTRL_PIN(34, "GPIO_34"),
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PINCTRL_PIN(35, "GPIO_35"),
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PINCTRL_PIN(36, "GPIO_36"),
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PINCTRL_PIN(37, "GPIO_37"),
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PINCTRL_PIN(38, "GPIO_38"),
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PINCTRL_PIN(39, "GPIO_39"),
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PINCTRL_PIN(40, "GPIO_40"),
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PINCTRL_PIN(41, "GPIO_41"),
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PINCTRL_PIN(42, "GPIO_42"),
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PINCTRL_PIN(43, "GPIO_43"),
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PINCTRL_PIN(44, "GPIO_44"),
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PINCTRL_PIN(45, "GPIO_45"),
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PINCTRL_PIN(46, "GPIO_46"),
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PINCTRL_PIN(47, "GPIO_47"),
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PINCTRL_PIN(48, "GPIO_48"),
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PINCTRL_PIN(49, "GPIO_49"),
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PINCTRL_PIN(50, "GPIO_50"),
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PINCTRL_PIN(51, "GPIO_51"),
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PINCTRL_PIN(52, "GPIO_52"),
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PINCTRL_PIN(53, "GPIO_53"),
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PINCTRL_PIN(54, "GPIO_54"),
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PINCTRL_PIN(55, "GPIO_55"),
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PINCTRL_PIN(56, "GPIO_56"),
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PINCTRL_PIN(57, "GPIO_57"),
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PINCTRL_PIN(58, "GPIO_58"),
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PINCTRL_PIN(59, "GPIO_59"),
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PINCTRL_PIN(60, "GPIO_60"),
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PINCTRL_PIN(61, "GPIO_61"),
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PINCTRL_PIN(62, "GPIO_62"),
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PINCTRL_PIN(63, "GPIO_63"),
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PINCTRL_PIN(64, "GPIO_64"),
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PINCTRL_PIN(65, "GPIO_65"),
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PINCTRL_PIN(66, "GPIO_66"),
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PINCTRL_PIN(67, "GPIO_67"),
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PINCTRL_PIN(68, "GPIO_68"),
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PINCTRL_PIN(69, "SDC3_CLK"),
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PINCTRL_PIN(70, "SDC3_CMD"),
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PINCTRL_PIN(71, "SDC3_DATA"),
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};
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#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
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DECLARE_IPQ_GPIO_PINS(0);
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DECLARE_IPQ_GPIO_PINS(1);
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DECLARE_IPQ_GPIO_PINS(2);
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DECLARE_IPQ_GPIO_PINS(3);
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DECLARE_IPQ_GPIO_PINS(4);
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DECLARE_IPQ_GPIO_PINS(5);
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DECLARE_IPQ_GPIO_PINS(6);
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DECLARE_IPQ_GPIO_PINS(7);
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DECLARE_IPQ_GPIO_PINS(8);
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DECLARE_IPQ_GPIO_PINS(9);
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DECLARE_IPQ_GPIO_PINS(10);
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DECLARE_IPQ_GPIO_PINS(11);
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DECLARE_IPQ_GPIO_PINS(12);
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DECLARE_IPQ_GPIO_PINS(13);
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DECLARE_IPQ_GPIO_PINS(14);
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DECLARE_IPQ_GPIO_PINS(15);
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DECLARE_IPQ_GPIO_PINS(16);
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DECLARE_IPQ_GPIO_PINS(17);
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DECLARE_IPQ_GPIO_PINS(18);
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DECLARE_IPQ_GPIO_PINS(19);
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DECLARE_IPQ_GPIO_PINS(20);
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DECLARE_IPQ_GPIO_PINS(21);
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DECLARE_IPQ_GPIO_PINS(22);
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DECLARE_IPQ_GPIO_PINS(23);
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DECLARE_IPQ_GPIO_PINS(24);
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DECLARE_IPQ_GPIO_PINS(25);
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DECLARE_IPQ_GPIO_PINS(26);
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DECLARE_IPQ_GPIO_PINS(27);
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DECLARE_IPQ_GPIO_PINS(28);
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DECLARE_IPQ_GPIO_PINS(29);
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DECLARE_IPQ_GPIO_PINS(30);
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DECLARE_IPQ_GPIO_PINS(31);
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DECLARE_IPQ_GPIO_PINS(32);
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DECLARE_IPQ_GPIO_PINS(33);
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DECLARE_IPQ_GPIO_PINS(34);
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DECLARE_IPQ_GPIO_PINS(35);
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DECLARE_IPQ_GPIO_PINS(36);
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DECLARE_IPQ_GPIO_PINS(37);
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DECLARE_IPQ_GPIO_PINS(38);
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DECLARE_IPQ_GPIO_PINS(39);
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DECLARE_IPQ_GPIO_PINS(40);
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DECLARE_IPQ_GPIO_PINS(41);
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DECLARE_IPQ_GPIO_PINS(42);
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DECLARE_IPQ_GPIO_PINS(43);
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DECLARE_IPQ_GPIO_PINS(44);
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DECLARE_IPQ_GPIO_PINS(45);
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DECLARE_IPQ_GPIO_PINS(46);
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DECLARE_IPQ_GPIO_PINS(47);
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DECLARE_IPQ_GPIO_PINS(48);
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DECLARE_IPQ_GPIO_PINS(49);
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DECLARE_IPQ_GPIO_PINS(50);
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DECLARE_IPQ_GPIO_PINS(51);
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DECLARE_IPQ_GPIO_PINS(52);
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DECLARE_IPQ_GPIO_PINS(53);
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DECLARE_IPQ_GPIO_PINS(54);
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DECLARE_IPQ_GPIO_PINS(55);
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DECLARE_IPQ_GPIO_PINS(56);
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DECLARE_IPQ_GPIO_PINS(57);
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DECLARE_IPQ_GPIO_PINS(58);
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DECLARE_IPQ_GPIO_PINS(59);
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DECLARE_IPQ_GPIO_PINS(60);
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DECLARE_IPQ_GPIO_PINS(61);
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DECLARE_IPQ_GPIO_PINS(62);
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DECLARE_IPQ_GPIO_PINS(63);
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DECLARE_IPQ_GPIO_PINS(64);
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DECLARE_IPQ_GPIO_PINS(65);
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DECLARE_IPQ_GPIO_PINS(66);
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DECLARE_IPQ_GPIO_PINS(67);
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DECLARE_IPQ_GPIO_PINS(68);
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static const unsigned int sdc3_clk_pins[] = { 69 };
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static const unsigned int sdc3_cmd_pins[] = { 70 };
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static const unsigned int sdc3_data_pins[] = { 71 };
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#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
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{ \
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.grp = PINCTRL_PINGROUP("gpio" #id, \
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gpio##id##_pins, \
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ARRAY_SIZE(gpio##id##_pins)), \
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.funcs = (int[]){ \
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IPQ_MUX_gpio, \
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IPQ_MUX_##f1, \
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IPQ_MUX_##f2, \
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IPQ_MUX_##f3, \
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IPQ_MUX_##f4, \
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IPQ_MUX_##f5, \
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IPQ_MUX_##f6, \
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IPQ_MUX_##f7, \
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IPQ_MUX_##f8, \
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IPQ_MUX_##f9, \
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IPQ_MUX_##f10, \
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}, \
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.nfuncs = 11, \
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.ctl_reg = 0x1000 + 0x10 * id, \
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.io_reg = 0x1004 + 0x10 * id, \
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.intr_cfg_reg = 0x1008 + 0x10 * id, \
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.intr_status_reg = 0x100c + 0x10 * id, \
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.intr_target_reg = 0x400 + 0x4 * id, \
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.mux_bit = 2, \
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.pull_bit = 0, \
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.drv_bit = 6, \
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.oe_bit = 9, \
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.in_bit = 0, \
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.out_bit = 1, \
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.intr_enable_bit = 0, \
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.intr_status_bit = 0, \
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.intr_ack_high = 1, \
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.intr_target_bit = 0, \
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.intr_target_kpss_val = 4, \
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.intr_raw_status_bit = 3, \
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.intr_polarity_bit = 1, \
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.intr_detection_bit = 2, \
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.intr_detection_width = 1, \
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}
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#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
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{ \
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.grp = PINCTRL_PINGROUP(#pg_name, \
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pg_name##_pins, \
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ARRAY_SIZE(pg_name##_pins)), \
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.ctl_reg = ctl, \
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.io_reg = 0, \
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.intr_cfg_reg = 0, \
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.intr_status_reg = 0, \
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.intr_target_reg = 0, \
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.mux_bit = -1, \
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.pull_bit = pull, \
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.drv_bit = drv, \
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.oe_bit = -1, \
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.in_bit = -1, \
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.out_bit = -1, \
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.intr_enable_bit = -1, \
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.intr_status_bit = -1, \
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.intr_target_bit = -1, \
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.intr_target_kpss_val = -1, \
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.intr_raw_status_bit = -1, \
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.intr_polarity_bit = -1, \
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.intr_detection_bit = -1, \
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.intr_detection_width = -1, \
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}
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enum ipq8064_functions {
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IPQ_MUX_gpio,
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IPQ_MUX_mdio,
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IPQ_MUX_mi2s,
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IPQ_MUX_pdm,
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IPQ_MUX_ssbi,
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IPQ_MUX_spmi,
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IPQ_MUX_audio_pcm,
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IPQ_MUX_gsbi1,
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IPQ_MUX_gsbi2,
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IPQ_MUX_gsbi4,
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IPQ_MUX_gsbi5,
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IPQ_MUX_gsbi5_spi_cs1,
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IPQ_MUX_gsbi5_spi_cs2,
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IPQ_MUX_gsbi5_spi_cs3,
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IPQ_MUX_gsbi6,
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IPQ_MUX_gsbi7,
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IPQ_MUX_nss_spi,
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IPQ_MUX_sdc1,
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IPQ_MUX_spdif,
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IPQ_MUX_nand,
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IPQ_MUX_tsif1,
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IPQ_MUX_tsif2,
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IPQ_MUX_usb_fs_n,
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IPQ_MUX_usb_fs,
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IPQ_MUX_usb2_hsic,
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IPQ_MUX_rgmii2,
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IPQ_MUX_sata,
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IPQ_MUX_pcie1_rst,
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IPQ_MUX_pcie1_prsnt,
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IPQ_MUX_pcie1_pwrflt,
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IPQ_MUX_pcie1_pwren_n,
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IPQ_MUX_pcie1_pwren,
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IPQ_MUX_pcie1_clk_req,
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IPQ_MUX_pcie2_rst,
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IPQ_MUX_pcie2_prsnt,
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IPQ_MUX_pcie2_pwrflt,
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IPQ_MUX_pcie2_pwren_n,
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IPQ_MUX_pcie2_pwren,
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IPQ_MUX_pcie2_clk_req,
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IPQ_MUX_pcie3_rst,
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IPQ_MUX_pcie3_prsnt,
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IPQ_MUX_pcie3_pwrflt,
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IPQ_MUX_pcie3_pwren_n,
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IPQ_MUX_pcie3_pwren,
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IPQ_MUX_pcie3_clk_req,
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IPQ_MUX_ps_hold,
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IPQ_MUX_NA,
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};
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static const char * const gpio_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
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"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
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"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
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"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
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"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
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"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
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"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
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"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
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"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
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"gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
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};
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static const char * const mdio_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
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};
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static const char * const mi2s_groups[] = {
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"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
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"gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
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};
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static const char * const pdm_groups[] = {
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"gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
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"gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
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"gpio59",
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};
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static const char * const ssbi_groups[] = {
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"gpio10", "gpio11",
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};
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static const char * const spmi_groups[] = {
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"gpio10", "gpio11",
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};
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static const char * const audio_pcm_groups[] = {
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"gpio14", "gpio15", "gpio16", "gpio17",
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};
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static const char * const gsbi1_groups[] = {
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"gpio51", "gpio52", "gpio53", "gpio54",
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};
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static const char * const gsbi2_groups[] = {
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"gpio22", "gpio23", "gpio24", "gpio25",
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};
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static const char * const gsbi4_groups[] = {
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"gpio10", "gpio11", "gpio12", "gpio13",
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};
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static const char * const gsbi5_groups[] = {
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"gpio18", "gpio19", "gpio20", "gpio21",
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};
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static const char * const gsbi5_spi_cs1_groups[] = {
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"gpio6", "gpio61",
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};
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static const char * const gsbi5_spi_cs2_groups[] = {
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"gpio7", "gpio62",
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};
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static const char * const gsbi5_spi_cs3_groups[] = {
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"gpio2",
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};
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static const char * const gsbi6_groups[] = {
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"gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
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"gpio57", "gpio58",
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};
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static const char * const gsbi7_groups[] = {
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"gpio6", "gpio7", "gpio8", "gpio9",
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};
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static const char * const nss_spi_groups[] = {
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"gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
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"gpio57", "gpio58",
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};
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static const char * const sdc1_groups[] = {
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"gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
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"gpio44", "gpio45", "gpio46", "gpio47",
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};
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static const char * const spdif_groups[] = {
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"gpio10", "gpio48",
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};
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static const char * const nand_groups[] = {
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"gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
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"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
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"gpio46", "gpio47",
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};
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static const char * const tsif1_groups[] = {
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"gpio55", "gpio56", "gpio57", "gpio58",
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};
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static const char * const tsif2_groups[] = {
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"gpio59", "gpio60", "gpio61", "gpio62",
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};
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static const char * const usb_fs_n_groups[] = {
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"gpio6",
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};
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static const char * const usb_fs_groups[] = {
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"gpio6", "gpio7", "gpio8",
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};
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static const char * const usb2_hsic_groups[] = {
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"gpio67", "gpio68",
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};
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static const char * const rgmii2_groups[] = {
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"gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
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"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
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};
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static const char * const sata_groups[] = {
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"gpio10",
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};
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static const char * const pcie1_rst_groups[] = {
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"gpio3",
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};
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static const char * const pcie1_prsnt_groups[] = {
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"gpio3", "gpio11",
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};
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static const char * const pcie1_pwren_n_groups[] = {
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"gpio4", "gpio12",
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};
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static const char * const pcie1_pwren_groups[] = {
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"gpio4", "gpio12",
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};
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static const char * const pcie1_pwrflt_groups[] = {
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"gpio5", "gpio13",
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};
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static const char * const pcie1_clk_req_groups[] = {
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"gpio5",
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};
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static const char * const pcie2_rst_groups[] = {
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"gpio48",
|
|
};
|
|
|
|
static const char * const pcie2_prsnt_groups[] = {
|
|
"gpio11", "gpio48",
|
|
};
|
|
|
|
static const char * const pcie2_pwren_n_groups[] = {
|
|
"gpio12", "gpio49",
|
|
};
|
|
|
|
static const char * const pcie2_pwren_groups[] = {
|
|
"gpio12", "gpio49",
|
|
};
|
|
|
|
static const char * const pcie2_pwrflt_groups[] = {
|
|
"gpio13", "gpio50",
|
|
};
|
|
|
|
static const char * const pcie2_clk_req_groups[] = {
|
|
"gpio50",
|
|
};
|
|
|
|
static const char * const pcie3_rst_groups[] = {
|
|
"gpio63",
|
|
};
|
|
|
|
static const char * const pcie3_prsnt_groups[] = {
|
|
"gpio11",
|
|
};
|
|
|
|
static const char * const pcie3_pwren_n_groups[] = {
|
|
"gpio12",
|
|
};
|
|
|
|
static const char * const pcie3_pwren_groups[] = {
|
|
"gpio12",
|
|
};
|
|
|
|
static const char * const pcie3_pwrflt_groups[] = {
|
|
"gpio13",
|
|
};
|
|
|
|
static const char * const pcie3_clk_req_groups[] = {
|
|
"gpio65",
|
|
};
|
|
|
|
static const char * const ps_hold_groups[] = {
|
|
"gpio26",
|
|
};
|
|
|
|
static const struct pinfunction ipq8064_functions[] = {
|
|
IPQ_PIN_FUNCTION(gpio),
|
|
IPQ_PIN_FUNCTION(mdio),
|
|
IPQ_PIN_FUNCTION(ssbi),
|
|
IPQ_PIN_FUNCTION(spmi),
|
|
IPQ_PIN_FUNCTION(mi2s),
|
|
IPQ_PIN_FUNCTION(pdm),
|
|
IPQ_PIN_FUNCTION(audio_pcm),
|
|
IPQ_PIN_FUNCTION(gsbi1),
|
|
IPQ_PIN_FUNCTION(gsbi2),
|
|
IPQ_PIN_FUNCTION(gsbi4),
|
|
IPQ_PIN_FUNCTION(gsbi5),
|
|
IPQ_PIN_FUNCTION(gsbi5_spi_cs1),
|
|
IPQ_PIN_FUNCTION(gsbi5_spi_cs2),
|
|
IPQ_PIN_FUNCTION(gsbi5_spi_cs3),
|
|
IPQ_PIN_FUNCTION(gsbi6),
|
|
IPQ_PIN_FUNCTION(gsbi7),
|
|
IPQ_PIN_FUNCTION(nss_spi),
|
|
IPQ_PIN_FUNCTION(sdc1),
|
|
IPQ_PIN_FUNCTION(spdif),
|
|
IPQ_PIN_FUNCTION(nand),
|
|
IPQ_PIN_FUNCTION(tsif1),
|
|
IPQ_PIN_FUNCTION(tsif2),
|
|
IPQ_PIN_FUNCTION(usb_fs_n),
|
|
IPQ_PIN_FUNCTION(usb_fs),
|
|
IPQ_PIN_FUNCTION(usb2_hsic),
|
|
IPQ_PIN_FUNCTION(rgmii2),
|
|
IPQ_PIN_FUNCTION(sata),
|
|
IPQ_PIN_FUNCTION(pcie1_rst),
|
|
IPQ_PIN_FUNCTION(pcie1_prsnt),
|
|
IPQ_PIN_FUNCTION(pcie1_pwren_n),
|
|
IPQ_PIN_FUNCTION(pcie1_pwren),
|
|
IPQ_PIN_FUNCTION(pcie1_pwrflt),
|
|
IPQ_PIN_FUNCTION(pcie1_clk_req),
|
|
IPQ_PIN_FUNCTION(pcie2_rst),
|
|
IPQ_PIN_FUNCTION(pcie2_prsnt),
|
|
IPQ_PIN_FUNCTION(pcie2_pwren_n),
|
|
IPQ_PIN_FUNCTION(pcie2_pwren),
|
|
IPQ_PIN_FUNCTION(pcie2_pwrflt),
|
|
IPQ_PIN_FUNCTION(pcie2_clk_req),
|
|
IPQ_PIN_FUNCTION(pcie3_rst),
|
|
IPQ_PIN_FUNCTION(pcie3_prsnt),
|
|
IPQ_PIN_FUNCTION(pcie3_pwren_n),
|
|
IPQ_PIN_FUNCTION(pcie3_pwren),
|
|
IPQ_PIN_FUNCTION(pcie3_pwrflt),
|
|
IPQ_PIN_FUNCTION(pcie3_clk_req),
|
|
IPQ_PIN_FUNCTION(ps_hold),
|
|
};
|
|
|
|
static const struct msm_pingroup ipq8064_groups[] = {
|
|
PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
|
|
PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
|
|
PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
|
|
PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
|
|
PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
|
|
PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
|
|
PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
|
|
SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
|
|
SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
|
|
SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
|
|
};
|
|
|
|
#define NUM_GPIO_PINGROUPS 69
|
|
|
|
static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
|
|
.pins = ipq8064_pins,
|
|
.npins = ARRAY_SIZE(ipq8064_pins),
|
|
.functions = ipq8064_functions,
|
|
.nfunctions = ARRAY_SIZE(ipq8064_functions),
|
|
.groups = ipq8064_groups,
|
|
.ngroups = ARRAY_SIZE(ipq8064_groups),
|
|
.ngpios = NUM_GPIO_PINGROUPS,
|
|
};
|
|
|
|
static int ipq8064_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
|
|
}
|
|
|
|
static const struct of_device_id ipq8064_pinctrl_of_match[] = {
|
|
{ .compatible = "qcom,ipq8064-pinctrl", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver ipq8064_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "ipq8064-pinctrl",
|
|
.of_match_table = ipq8064_pinctrl_of_match,
|
|
},
|
|
.probe = ipq8064_pinctrl_probe,
|
|
.remove_new = msm_pinctrl_remove,
|
|
};
|
|
|
|
static int __init ipq8064_pinctrl_init(void)
|
|
{
|
|
return platform_driver_register(&ipq8064_pinctrl_driver);
|
|
}
|
|
arch_initcall(ipq8064_pinctrl_init);
|
|
|
|
static void __exit ipq8064_pinctrl_exit(void)
|
|
{
|
|
platform_driver_unregister(&ipq8064_pinctrl_driver);
|
|
}
|
|
module_exit(ipq8064_pinctrl_exit);
|
|
|
|
MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
|
MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
|