Christoph Hellwig 1db7a7ca5a riscv: cleanup send_ipi_mask ... Use the special barriers for atomic bitops to make the intention a little more clear, and use riscv_cpuid_to_hartid_mask instead of open coding it. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-09-05 01:44:37 -07:00
..
boot	riscv: dts: fu540-c000: drop "timebase-frequency"	2019-07-31 12:26:10 -07:00
configs	riscv: defconfig: Update the defconfig	2019-08-13 19:26:42 -07:00
include	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
kernel	riscv: cleanup send_ipi_mask	2019-09-05 01:44:37 -07:00
lib	riscv: Using CSR numbers to access CSRs	2019-08-30 11:04:19 -07:00
mm	RISC-V: Implement sparsemem	2019-08-30 11:10:37 -07:00
net	bpf, riscv: Enable zext optimization for more RV64G ALU ops	2019-07-05 23:55:41 +02:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	riscv: Add perf callchain support	2019-09-04 12:43:00 -07:00