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edcbe90f12
kvm_vm_ioctl_check_extension(): Return 1 if KVM_CAP_SET_GUEST_DEBUG is been checked. kvm_arch_vcpu_ioctl_set_guest_debug(): Update the guest_debug flags from userspace accordingly. Route the breakpoint exceptions to HS mode if the VCPU is being debugged by userspace, by clearing the corresponding bit in hedeleg. Initialize the hedeleg configuration in kvm_riscv_vcpu_setup_config(). Write the actual CSR in kvm_arch_vcpu_load(). Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240402062628.5425-2-duchao@eswincomputing.com Signed-off-by: Anup Patel <anup@brainfault.org>
125 lines
2.5 KiB
C
125 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/cpufeature.h>
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#include <asm/sbi.h>
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long kvm_arch_dev_ioctl(struct file *filp,
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unsigned int ioctl, unsigned long arg)
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{
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return -EINVAL;
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}
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int kvm_arch_hardware_enable(void)
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{
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csr_write(CSR_HEDELEG, KVM_HEDELEG_DEFAULT);
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csr_write(CSR_HIDELEG, KVM_HIDELEG_DEFAULT);
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/* VS should access only the time counter directly. Everything else should trap */
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csr_write(CSR_HCOUNTEREN, 0x02);
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csr_write(CSR_HVIP, 0);
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kvm_riscv_aia_enable();
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return 0;
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}
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void kvm_arch_hardware_disable(void)
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{
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kvm_riscv_aia_disable();
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/*
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* After clearing the hideleg CSR, the host kernel will receive
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* spurious interrupts if hvip CSR has pending interrupts and the
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* corresponding enable bits in vsie CSR are asserted. To avoid it,
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* hvip CSR and vsie CSR must be cleared before clearing hideleg CSR.
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*/
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csr_write(CSR_VSIE, 0);
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csr_write(CSR_HVIP, 0);
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csr_write(CSR_HEDELEG, 0);
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csr_write(CSR_HIDELEG, 0);
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}
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static int __init riscv_kvm_init(void)
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{
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int rc;
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const char *str;
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if (!riscv_isa_extension_available(NULL, h)) {
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kvm_info("hypervisor extension not available\n");
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return -ENODEV;
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}
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if (sbi_spec_is_0_1()) {
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kvm_info("require SBI v0.2 or higher\n");
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return -ENODEV;
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}
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if (!sbi_probe_extension(SBI_EXT_RFENCE)) {
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kvm_info("require SBI RFENCE extension\n");
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return -ENODEV;
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}
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kvm_riscv_gstage_mode_detect();
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kvm_riscv_gstage_vmid_detect();
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rc = kvm_riscv_aia_init();
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if (rc && rc != -ENODEV)
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return rc;
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kvm_info("hypervisor extension available\n");
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switch (kvm_riscv_gstage_mode()) {
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case HGATP_MODE_SV32X4:
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str = "Sv32x4";
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break;
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case HGATP_MODE_SV39X4:
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str = "Sv39x4";
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break;
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case HGATP_MODE_SV48X4:
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str = "Sv48x4";
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break;
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case HGATP_MODE_SV57X4:
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str = "Sv57x4";
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break;
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default:
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return -ENODEV;
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}
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kvm_info("using %s G-stage page table format\n", str);
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kvm_info("VMID %ld bits available\n", kvm_riscv_gstage_vmid_bits());
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if (kvm_riscv_aia_available())
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kvm_info("AIA available with %d guest external interrupts\n",
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kvm_riscv_aia_nr_hgei);
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rc = kvm_init(sizeof(struct kvm_vcpu), 0, THIS_MODULE);
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if (rc) {
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kvm_riscv_aia_exit();
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return rc;
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}
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return 0;
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}
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module_init(riscv_kvm_init);
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static void __exit riscv_kvm_exit(void)
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{
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kvm_riscv_aia_exit();
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kvm_exit();
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}
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module_exit(riscv_kvm_exit);
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