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9d9659b6c0
This is my second attempt to make this enum generally available. The first attempt added MMCIF_PROGRESS_* to include/linux/mmc/sh_mmcif.h. However this is not sufficiently generic as the enum will be used by SDHI boot code. Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
72 lines
2 KiB
C
72 lines
2 KiB
C
/*
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* sh7724 MMCIF loader
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*
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* Copyright (C) 2010 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/mmc/boot.h>
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#include <mach/romimage.h>
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#define MMCIF_BASE (void __iomem *)0xa4ca0000
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#define MSTPCR2 0xa4150038
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#define PTWCR 0xa4050146
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#define PTXCR 0xa4050148
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#define PSELA 0xa405014e
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#define PSELE 0xa4050156
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#define HIZCRC 0xa405015c
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#define DRVCRA 0xa405018a
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/* SH7724 specific MMCIF loader
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*
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* loads the romImage from an MMC card starting from block 512
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* use the following line to write the romImage to an MMC card
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* # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
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*/
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asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
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{
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mmcif_update_progress(MMC_PROGRESS_ENTER);
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/* enable clock to the MMCIF hardware block */
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__raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
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/* setup pins D7-D0 */
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__raw_writew(0x0000, PTWCR);
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/* setup pins MMC_CLK, MMC_CMD */
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__raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
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/* select D3-D0 pin function */
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__raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
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/* select D7-D4 pin function */
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__raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
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/* disable Hi-Z for the MMC pins */
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__raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
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/* high drive capability for MMC pins */
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__raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
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mmcif_update_progress(MMC_PROGRESS_INIT);
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/* setup MMCIF hardware */
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sh_mmcif_boot_init(MMCIF_BASE);
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mmcif_update_progress(MMC_PROGRESS_LOAD);
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/* load kernel via MMCIF interface */
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sh_mmcif_boot_do_read(MMCIF_BASE, 512,
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(no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
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buf);
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/* disable clock to the MMCIF hardware block */
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__raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
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mmcif_update_progress(MMC_PROGRESS_DONE);
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}
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