mirror of
https://github.com/torvalds/linux
synced 2024-09-21 19:47:35 +00:00
9e3f544d79
When using the Java Extension Module hardware, a Java stack underflow or overflow trap may cause the system to enter an infinite exception loop. Although there's no kernel support for the Java hardware yet, we need to be able to recover from this situation and keep the system running. This patch adds code to detect and fixup this situation in the critical exception handler and terminate the faulting process. We may have to rethink how to handle this more gracefully when the necessary kernel support for hardware-accelerated Java is added. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
875 lines
18 KiB
ArmAsm
875 lines
18 KiB
ArmAsm
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* This file contains the low-level entry-points into the kernel, that is,
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* exception handlers, debug trap handlers, interrupt handlers and the
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* system call handler.
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*/
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#include <linux/errno.h>
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#include <asm/asm.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/ocd.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#ifdef CONFIG_PREEMPT
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# define preempt_stop mask_interrupts
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#else
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# define preempt_stop
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# define fault_resume_kernel fault_restore_all
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#endif
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#define __MASK(x) ((1 << (x)) - 1)
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#define IRQ_MASK ((__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) | \
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(__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT))
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.section .ex.text,"ax",@progbits
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.align 2
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exception_vectors:
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bral handle_critical
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.align 2
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bral handle_critical
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.align 2
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bral do_bus_error_write
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.align 2
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bral do_bus_error_read
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.align 2
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bral do_nmi_ll
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral handle_debug
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral do_fpe_ll
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.align 2
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bral do_illegal_opcode_ll
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_address_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral handle_protection_fault
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.align 2
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bral do_dtlb_modified
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#define tlbmiss_save pushm r0-r3
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#define tlbmiss_restore popm r0-r3
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.org 0x50
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.global itlb_miss
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itlb_miss:
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tlbmiss_save
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rjmp tlb_miss_common
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.org 0x60
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dtlb_miss_read:
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tlbmiss_save
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rjmp tlb_miss_common
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.org 0x70
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dtlb_miss_write:
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tlbmiss_save
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.global tlb_miss_common
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.align 2
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tlb_miss_common:
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mfsr r0, SYSREG_TLBEAR
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mfsr r1, SYSREG_PTBR
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/*
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* First level lookup: The PGD contains virtual pointers to
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* the second-level page tables, but they may be NULL if not
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* present.
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*/
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pgtbl_lookup:
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lsr r2, r0, PGDIR_SHIFT
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ld.w r3, r1[r2 << 2]
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bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
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cp.w r3, 0
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breq page_table_not_present
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/* Second level lookup */
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ld.w r2, r3[r1 << 2]
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mfsr r0, SYSREG_TLBARLO
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bld r2, _PAGE_BIT_PRESENT
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brcc page_not_present
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/* Mark the page as accessed */
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sbr r2, _PAGE_BIT_ACCESSED
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st.w r3[r1 << 2], r2
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/* Drop software flags */
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andl r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
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mtsr SYSREG_TLBELO, r2
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/* Figure out which entry we want to replace */
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mfsr r1, SYSREG_MMUCR
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clz r2, r0
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brcc 1f
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mov r3, -1 /* All entries have been accessed, */
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mov r2, 0 /* so start at 0 */
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mtsr SYSREG_TLBARLO, r3 /* and reset TLBAR */
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1: bfins r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
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mtsr SYSREG_MMUCR, r1
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tlbw
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tlbmiss_restore
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rete
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/* The slow path of the TLB miss handler */
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.align 2
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page_table_not_present:
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/* Do we need to synchronize with swapper_pg_dir? */
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bld r0, 31
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brcs sync_with_swapper_pg_dir
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page_not_present:
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tlbmiss_restore
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_page_fault
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rjmp ret_from_exception
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.align 2
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sync_with_swapper_pg_dir:
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/*
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* If swapper_pg_dir contains a non-NULL second-level page
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* table pointer, copy it into the current PGD. If not, we
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* must handle it as a full-blown page fault.
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*
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* Jumping back to pgtbl_lookup causes an unnecessary lookup,
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* but it is guaranteed to be a cache hit, it won't happen
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* very often, and we absolutely do not want to sacrifice any
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* performance in the fast path in order to improve this.
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*/
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mov r1, lo(swapper_pg_dir)
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orh r1, hi(swapper_pg_dir)
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ld.w r3, r1[r2 << 2]
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cp.w r3, 0
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breq page_not_present
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mfsr r1, SYSREG_PTBR
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st.w r1[r2 << 2], r3
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rjmp pgtbl_lookup
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/*
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* We currently have two bytes left at this point until we
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* crash into the system call handler...
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*
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* Don't worry, the assembler will let us know.
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*/
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/* --- System Call --- */
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.org 0x100
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system_call:
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#ifdef CONFIG_PREEMPT
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mask_interrupts
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#endif
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pushm r12 /* r12_orig */
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stmts --sp, r0-lr
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mfsr r0, SYSREG_RAR_SUP
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mfsr r1, SYSREG_RSR_SUP
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#ifdef CONFIG_PREEMPT
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unmask_interrupts
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#endif
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zero_fp
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stm --sp, r0-r1
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/* check for syscall tracing */
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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bld r1, TIF_SYSCALL_TRACE
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brcs syscall_trace_enter
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syscall_trace_cont:
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cp.w r8, NR_syscalls
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brhs syscall_badsys
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lddpc lr, syscall_table_addr
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ld.w lr, lr[r8 << 2]
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mov r8, r5 /* 5th argument (6th is pushed by stub) */
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icall lr
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.global syscall_return
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syscall_return:
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get_thread_info r0
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mask_interrupts /* make sure we don't miss an interrupt
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setting need_resched or sigpending
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between sampling and the rets */
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/* Store the return value so that the correct value is loaded below */
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stdsp sp[REG_R12], r12
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ld.w r1, r0[TI_flags]
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andl r1, _TIF_ALLWORK_MASK, COH
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brne syscall_exit_work
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syscall_exit_cont:
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popm r8-r9
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mtsr SYSREG_RAR_SUP, r8
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mtsr SYSREG_RSR_SUP, r9
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ldmts sp++, r0-lr
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sub sp, -4 /* r12_orig */
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rets
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.align 2
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syscall_table_addr:
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.long sys_call_table
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syscall_badsys:
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mov r12, -ENOSYS
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rjmp syscall_return
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.global ret_from_fork
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ret_from_fork:
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rcall schedule_tail
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/* check for syscall tracing */
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get_thread_info r0
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ld.w r1, r0[TI_flags]
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andl r1, _TIF_ALLWORK_MASK, COH
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brne syscall_exit_work
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rjmp syscall_exit_cont
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syscall_trace_enter:
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pushm r8-r12
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rcall syscall_trace
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popm r8-r12
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rjmp syscall_trace_cont
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syscall_exit_work:
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bld r1, TIF_SYSCALL_TRACE
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brcc 1f
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unmask_interrupts
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rcall syscall_trace
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mask_interrupts
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ld.w r1, r0[TI_flags]
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1: bld r1, TIF_NEED_RESCHED
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brcc 2f
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unmask_interrupts
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rcall schedule
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp 1b
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2: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
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tst r1, r2
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breq 3f
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unmask_interrupts
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mov r12, sp
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mov r11, r0
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rcall do_notify_resume
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mask_interrupts
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ld.w r1, r0[TI_flags]
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rjmp 1b
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3: bld r1, TIF_BREAKPOINT
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brcc syscall_exit_cont
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rjmp enter_monitor_mode
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/* This function expects to find offending PC in SYSREG_RAR_EX */
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.type save_full_context_ex, @function
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.align 2
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save_full_context_ex:
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mfsr r11, SYSREG_RAR_EX
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sub r9, pc, . - debug_trampoline
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mfsr r8, SYSREG_RSR_EX
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cp.w r9, r11
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breq 3f
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mov r12, r8
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andh r8, (MODE_MASK >> 16), COH
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brne 2f
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1: pushm r11, r12 /* PC and SR */
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unmask_exceptions
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ret r12
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2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
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stdsp sp[4], r10 /* replace saved SP */
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rjmp 1b
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/*
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* The debug handler set up a trampoline to make us
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* automatically enter monitor mode upon return, but since
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* we're saving the full context, we must assume that the
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* exception handler might want to alter the return address
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* and/or status register. So we need to restore the original
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* context and enter monitor mode manually after the exception
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* has been handled.
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*/
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3: get_thread_info r8
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ld.w r11, r8[TI_rar_saved]
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ld.w r12, r8[TI_rsr_saved]
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rjmp 1b
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.size save_full_context_ex, . - save_full_context_ex
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/* Low-level exception handlers */
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handle_critical:
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/*
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* AT32AP700x errata:
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*
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* After a Java stack overflow or underflow trap, any CPU
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* memory access may cause erratic behavior. This will happen
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* when the four least significant bits of the JOSP system
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* register contains any value between 9 and 15 (inclusive).
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*
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* Possible workarounds:
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* - Don't use the Java Extension Module
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* - Ensure that the stack overflow and underflow trap
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* handlers do not do any memory access or trigger any
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* exceptions before the overflow/underflow condition is
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* cleared (by incrementing or decrementing the JOSP)
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* - Make sure that JOSP does not contain any problematic
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* value before doing any exception or interrupt
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* processing.
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* - Set up a critical exception handler which writes a
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* known-to-be-safe value, e.g. 4, to JOSP before doing
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* any further processing.
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*
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* We'll use the last workaround for now since we cannot
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* guarantee that user space processes don't use Java mode.
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* Non-well-behaving userland will be terminated with extreme
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* prejudice.
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*/
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#ifdef CONFIG_CPU_AT32AP700X
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/*
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* There's a chance we can't touch memory, so temporarily
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* borrow PTBR to save the stack pointer while we fix things
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* up...
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*/
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mtsr SYSREG_PTBR, sp
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mov sp, 4
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mtsr SYSREG_JOSP, sp
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mfsr sp, SYSREG_PTBR
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sub pc, -2
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/* Push most of pt_regs on stack. We'll do the rest later */
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sub sp, 4
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pushm r0-r12
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/* PTBR mirrors current_thread_info()->task->active_mm->pgd */
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get_thread_info r0
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ld.w r1, r0[TI_task]
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ld.w r2, r1[TSK_active_mm]
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ld.w r3, r2[MM_pgd]
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mtsr SYSREG_PTBR, r3
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#else
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sub sp, 4
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pushm r0-r12
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#endif
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sub r0, sp, -(14 * 4)
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mov r1, lr
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mfsr r2, SYSREG_RAR_EX
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mfsr r3, SYSREG_RSR_EX
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pushm r0-r3
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_critical_exception
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/* We should never get here... */
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bad_return:
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sub r12, pc, (. - 1f)
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bral panic
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.align 2
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1: .asciz "Return from critical exception!"
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.align 1
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do_bus_error_write:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mov r11, 1
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rjmp 1f
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do_bus_error_read:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mov r11, 0
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1: mfsr r12, SYSREG_BEAR
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mov r10, sp
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rcall do_bus_error
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rjmp ret_from_exception
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.align 1
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do_nmi_ll:
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sub sp, 4
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stmts --sp, r0-lr
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mfsr r9, SYSREG_RSR_NMI
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mfsr r8, SYSREG_RAR_NMI
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bfextu r0, r9, MODE_SHIFT, 3
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brne 2f
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1: pushm r8, r9 /* PC and SR */
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_nmi
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popm r8-r9
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mtsr SYSREG_RAR_NMI, r8
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tst r0, r0
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mtsr SYSREG_RSR_NMI, r9
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brne 3f
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ldmts sp++, r0-lr
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sub sp, -4 /* skip r12_orig */
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rete
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2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
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stdsp sp[4], r10 /* replace saved SP */
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rjmp 1b
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3: popm lr
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sub sp, -4 /* skip sp */
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popm r0-r12
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sub sp, -4 /* skip r12_orig */
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rete
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handle_address_fault:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_address_exception
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rjmp ret_from_exception
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handle_protection_fault:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_page_fault
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rjmp ret_from_exception
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.align 1
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do_illegal_opcode_ll:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_illegal_opcode
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rjmp ret_from_exception
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do_dtlb_modified:
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pushm r0-r3
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mfsr r1, SYSREG_TLBEAR
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mfsr r0, SYSREG_PTBR
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lsr r2, r1, PGDIR_SHIFT
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ld.w r0, r0[r2 << 2]
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lsl r1, (32 - PGDIR_SHIFT)
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lsr r1, (32 - PGDIR_SHIFT) + PAGE_SHIFT
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/* Translate to virtual address in P1 */
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andl r0, 0xf000
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sbr r0, 31
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add r2, r0, r1 << 2
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ld.w r3, r2[0]
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sbr r3, _PAGE_BIT_DIRTY
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mov r0, r3
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st.w r2[0], r3
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/* The page table is up-to-date. Update the TLB entry as well */
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andl r0, lo(_PAGE_FLAGS_HARDWARE_MASK)
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mtsr SYSREG_TLBELO, r0
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/* MMUCR[DRP] is updated automatically, so let's go... */
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tlbw
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popm r0-r3
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rete
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do_fpe_ll:
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sub sp, 4
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stmts --sp, r0-lr
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rcall save_full_context_ex
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unmask_interrupts
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mov r12, 26
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mov r11, sp
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rcall do_fpe
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rjmp ret_from_exception
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ret_from_exception:
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mask_interrupts
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lddsp r4, sp[REG_SR]
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andh r4, (MODE_MASK >> 16), COH
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brne fault_resume_kernel
|
|
|
|
get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
andl r1, _TIF_WORK_MASK, COH
|
|
brne fault_exit_work
|
|
|
|
fault_resume_user:
|
|
popm r8-r9
|
|
mask_exceptions
|
|
mtsr SYSREG_RAR_EX, r8
|
|
mtsr SYSREG_RSR_EX, r9
|
|
ldmts sp++, r0-lr
|
|
sub sp, -4
|
|
rete
|
|
|
|
fault_resume_kernel:
|
|
#ifdef CONFIG_PREEMPT
|
|
get_thread_info r0
|
|
ld.w r2, r0[TI_preempt_count]
|
|
cp.w r2, 0
|
|
brne 1f
|
|
ld.w r1, r0[TI_flags]
|
|
bld r1, TIF_NEED_RESCHED
|
|
brcc 1f
|
|
lddsp r4, sp[REG_SR]
|
|
bld r4, SYSREG_GM_OFFSET
|
|
brcs 1f
|
|
rcall preempt_schedule_irq
|
|
1:
|
|
#endif
|
|
|
|
popm r8-r9
|
|
mask_exceptions
|
|
mfsr r1, SYSREG_SR
|
|
mtsr SYSREG_RAR_EX, r8
|
|
mtsr SYSREG_RSR_EX, r9
|
|
popm lr
|
|
sub sp, -4 /* ignore SP */
|
|
popm r0-r12
|
|
sub sp, -4 /* ignore r12_orig */
|
|
rete
|
|
|
|
irq_exit_work:
|
|
/* Switch to exception mode so that we can share the same code. */
|
|
mfsr r8, SYSREG_SR
|
|
cbr r8, SYSREG_M0_OFFSET
|
|
orh r8, hi(SYSREG_BIT(M1) | SYSREG_BIT(M2))
|
|
mtsr SYSREG_SR, r8
|
|
sub pc, -2
|
|
get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
|
|
fault_exit_work:
|
|
bld r1, TIF_NEED_RESCHED
|
|
brcc 1f
|
|
unmask_interrupts
|
|
rcall schedule
|
|
mask_interrupts
|
|
ld.w r1, r0[TI_flags]
|
|
rjmp fault_exit_work
|
|
|
|
1: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
|
|
tst r1, r2
|
|
breq 2f
|
|
unmask_interrupts
|
|
mov r12, sp
|
|
mov r11, r0
|
|
rcall do_notify_resume
|
|
mask_interrupts
|
|
ld.w r1, r0[TI_flags]
|
|
rjmp fault_exit_work
|
|
|
|
2: bld r1, TIF_BREAKPOINT
|
|
brcc fault_resume_user
|
|
rjmp enter_monitor_mode
|
|
|
|
.section .kprobes.text, "ax", @progbits
|
|
.type handle_debug, @function
|
|
handle_debug:
|
|
sub sp, 4 /* r12_orig */
|
|
stmts --sp, r0-lr
|
|
mfsr r8, SYSREG_RAR_DBG
|
|
mfsr r9, SYSREG_RSR_DBG
|
|
unmask_exceptions
|
|
pushm r8-r9
|
|
bfextu r9, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
|
|
brne debug_fixup_regs
|
|
|
|
.Ldebug_fixup_cont:
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
rcall trace_hardirqs_off
|
|
#endif
|
|
mov r12, sp
|
|
rcall do_debug
|
|
mov sp, r12
|
|
|
|
lddsp r2, sp[REG_SR]
|
|
bfextu r3, r2, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
|
|
brne debug_resume_kernel
|
|
|
|
get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
mov r2, _TIF_DBGWORK_MASK
|
|
tst r1, r2
|
|
brne debug_exit_work
|
|
|
|
bld r1, TIF_SINGLE_STEP
|
|
brcc 1f
|
|
mfdr r4, OCD_DC
|
|
sbr r4, OCD_DC_SS_BIT
|
|
mtdr OCD_DC, r4
|
|
|
|
1: popm r10,r11
|
|
mask_exceptions
|
|
mtsr SYSREG_RSR_DBG, r11
|
|
mtsr SYSREG_RAR_DBG, r10
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
rcall trace_hardirqs_on
|
|
1:
|
|
#endif
|
|
ldmts sp++, r0-lr
|
|
sub sp, -4
|
|
retd
|
|
.size handle_debug, . - handle_debug
|
|
|
|
/* Mode of the trapped context is in r9 */
|
|
.type debug_fixup_regs, @function
|
|
debug_fixup_regs:
|
|
mfsr r8, SYSREG_SR
|
|
mov r10, r8
|
|
bfins r8, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
|
|
mtsr SYSREG_SR, r8
|
|
sub pc, -2
|
|
stdsp sp[REG_LR], lr
|
|
mtsr SYSREG_SR, r10
|
|
sub pc, -2
|
|
sub r8, sp, -FRAME_SIZE_FULL
|
|
stdsp sp[REG_SP], r8
|
|
rjmp .Ldebug_fixup_cont
|
|
.size debug_fixup_regs, . - debug_fixup_regs
|
|
|
|
.type debug_resume_kernel, @function
|
|
debug_resume_kernel:
|
|
mask_exceptions
|
|
popm r10, r11
|
|
mtsr SYSREG_RAR_DBG, r10
|
|
mtsr SYSREG_RSR_DBG, r11
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
bld r11, SYSREG_GM_OFFSET
|
|
brcc 1f
|
|
rcall trace_hardirqs_on
|
|
1:
|
|
#endif
|
|
mfsr r2, SYSREG_SR
|
|
mov r1, r2
|
|
bfins r2, r3, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
|
|
mtsr SYSREG_SR, r2
|
|
sub pc, -2
|
|
popm lr
|
|
mtsr SYSREG_SR, r1
|
|
sub pc, -2
|
|
sub sp, -4 /* skip SP */
|
|
popm r0-r12
|
|
sub sp, -4
|
|
retd
|
|
.size debug_resume_kernel, . - debug_resume_kernel
|
|
|
|
.type debug_exit_work, @function
|
|
debug_exit_work:
|
|
/*
|
|
* We must return from Monitor Mode using a retd, and we must
|
|
* not schedule since that involves the D bit in SR getting
|
|
* cleared by something other than the debug hardware. This
|
|
* may cause undefined behaviour according to the Architecture
|
|
* manual.
|
|
*
|
|
* So we fix up the return address and status and return to a
|
|
* stub below in Exception mode. From there, we can follow the
|
|
* normal exception return path.
|
|
*
|
|
* The real return address and status registers are stored on
|
|
* the stack in the way the exception return path understands,
|
|
* so no need to fix anything up there.
|
|
*/
|
|
sub r8, pc, . - fault_exit_work
|
|
mtsr SYSREG_RAR_DBG, r8
|
|
mov r9, 0
|
|
orh r9, hi(SR_EM | SR_GM | MODE_EXCEPTION)
|
|
mtsr SYSREG_RSR_DBG, r9
|
|
sub pc, -2
|
|
retd
|
|
.size debug_exit_work, . - debug_exit_work
|
|
|
|
.set rsr_int0, SYSREG_RSR_INT0
|
|
.set rsr_int1, SYSREG_RSR_INT1
|
|
.set rsr_int2, SYSREG_RSR_INT2
|
|
.set rsr_int3, SYSREG_RSR_INT3
|
|
.set rar_int0, SYSREG_RAR_INT0
|
|
.set rar_int1, SYSREG_RAR_INT1
|
|
.set rar_int2, SYSREG_RAR_INT2
|
|
.set rar_int3, SYSREG_RAR_INT3
|
|
|
|
.macro IRQ_LEVEL level
|
|
.type irq_level\level, @function
|
|
irq_level\level:
|
|
sub sp, 4 /* r12_orig */
|
|
stmts --sp,r0-lr
|
|
mfsr r8, rar_int\level
|
|
mfsr r9, rsr_int\level
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
sub r11, pc, (. - system_call)
|
|
cp.w r11, r8
|
|
breq 4f
|
|
#endif
|
|
|
|
pushm r8-r9
|
|
|
|
mov r11, sp
|
|
mov r12, \level
|
|
|
|
rcall do_IRQ
|
|
|
|
lddsp r4, sp[REG_SR]
|
|
bfextu r4, r4, SYSREG_M0_OFFSET, 3
|
|
cp.w r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
|
|
breq 2f
|
|
cp.w r4, MODE_USER >> SYSREG_M0_OFFSET
|
|
#ifdef CONFIG_PREEMPT
|
|
brne 3f
|
|
#else
|
|
brne 1f
|
|
#endif
|
|
|
|
get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
andl r1, _TIF_WORK_MASK, COH
|
|
brne irq_exit_work
|
|
|
|
1:
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
|
rcall trace_hardirqs_on
|
|
#endif
|
|
popm r8-r9
|
|
mtsr rar_int\level, r8
|
|
mtsr rsr_int\level, r9
|
|
ldmts sp++,r0-lr
|
|
sub sp, -4 /* ignore r12_orig */
|
|
rete
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
4: mask_interrupts
|
|
mfsr r8, rsr_int\level
|
|
sbr r8, 16
|
|
mtsr rsr_int\level, r8
|
|
ldmts sp++, r0-lr
|
|
sub sp, -4 /* ignore r12_orig */
|
|
rete
|
|
#endif
|
|
|
|
2: get_thread_info r0
|
|
ld.w r1, r0[TI_flags]
|
|
bld r1, TIF_CPU_GOING_TO_SLEEP
|
|
#ifdef CONFIG_PREEMPT
|
|
brcc 3f
|
|
#else
|
|
brcc 1b
|
|
#endif
|
|
sub r1, pc, . - cpu_idle_skip_sleep
|
|
stdsp sp[REG_PC], r1
|
|
#ifdef CONFIG_PREEMPT
|
|
3: get_thread_info r0
|
|
ld.w r2, r0[TI_preempt_count]
|
|
cp.w r2, 0
|
|
brne 1b
|
|
ld.w r1, r0[TI_flags]
|
|
bld r1, TIF_NEED_RESCHED
|
|
brcc 1b
|
|
lddsp r4, sp[REG_SR]
|
|
bld r4, SYSREG_GM_OFFSET
|
|
brcs 1b
|
|
rcall preempt_schedule_irq
|
|
#endif
|
|
rjmp 1b
|
|
.endm
|
|
|
|
.section .irq.text,"ax",@progbits
|
|
|
|
.global irq_level0
|
|
.global irq_level1
|
|
.global irq_level2
|
|
.global irq_level3
|
|
IRQ_LEVEL 0
|
|
IRQ_LEVEL 1
|
|
IRQ_LEVEL 2
|
|
IRQ_LEVEL 3
|
|
|
|
.section .kprobes.text, "ax", @progbits
|
|
.type enter_monitor_mode, @function
|
|
enter_monitor_mode:
|
|
/*
|
|
* We need to enter monitor mode to do a single step. The
|
|
* monitor code will alter the return address so that we
|
|
* return directly to the user instead of returning here.
|
|
*/
|
|
breakpoint
|
|
rjmp breakpoint_failed
|
|
|
|
.size enter_monitor_mode, . - enter_monitor_mode
|
|
|
|
.type debug_trampoline, @function
|
|
.global debug_trampoline
|
|
debug_trampoline:
|
|
/*
|
|
* Save the registers on the stack so that the monitor code
|
|
* can find them easily.
|
|
*/
|
|
sub sp, 4 /* r12_orig */
|
|
stmts --sp, r0-lr
|
|
get_thread_info r0
|
|
ld.w r8, r0[TI_rar_saved]
|
|
ld.w r9, r0[TI_rsr_saved]
|
|
pushm r8-r9
|
|
|
|
/*
|
|
* The monitor code will alter the return address so we don't
|
|
* return here.
|
|
*/
|
|
breakpoint
|
|
rjmp breakpoint_failed
|
|
.size debug_trampoline, . - debug_trampoline
|
|
|
|
.type breakpoint_failed, @function
|
|
breakpoint_failed:
|
|
/*
|
|
* Something went wrong. Perhaps the debug hardware isn't
|
|
* enabled?
|
|
*/
|
|
lda.w r12, msg_breakpoint_failed
|
|
mov r11, sp
|
|
mov r10, 9 /* SIGKILL */
|
|
call die
|
|
1: rjmp 1b
|
|
|
|
msg_breakpoint_failed:
|
|
.asciz "Failed to enter Debug Mode"
|