linux/arch/arm/mach-omap1/sram.S
Jean Pihet b6338bdc83 ARM: 6649/1: omap: use fncpy to copy the PM code functions to SRAM
The new fncpy API is better suited* for copying some
code to SRAM at runtime. This patch changes the ad-hoc
code to the more generic fncpy API.

*: 1. fncpy ensures that the thumb mode bit is propagated,
   2. fncpy provides the security of type safety between the
     original function and the sram function pointer.

Tested OK on OMAP3 in low power modes (RET/OFF)
using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL.
Compile tested on OMAP1/2 using omap1_defconfig.

Boot tested on OMAP1 & OMAP2
Tested OK with suspend/resume on OMAP2420/n810

Boots fine on osk5912 and n800

Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Dave Martin <dave.martin@linaro.org>
Tested-by: Kevin Hilman <khilman@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-02-04 14:26:08 +00:00

59 lines
1.5 KiB
ArmAsm

/*
* linux/arch/arm/plat-omap/sram-fn.S
*
* Functions that need to be run in internal SRAM
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/io.h>
#include <mach/hardware.h>
.text
/*
* Reprograms ULPD and CKCTL.
*/
.align 3
ENTRY(omap1_sram_reprogram_clock)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
tst r0, #1 << 4 @ want lock mode?
beq newck @ nope
bic r0, r0, #1 << 4 @ else clear lock bit
strh r0, [r2] @ set dpll into bypass mode
orr r0, r0, #1 << 4 @ set lock bit again
newck:
strh r1, [r3] @ write new ckctl value
strh r0, [r2] @ write new dpll value
mov r4, #0x0700 @ let the clocks settle
orr r4, r4, #0x00ff
delay: sub r4, r4, #1
cmp r4, #0
bne delay
lock: ldrh r4, [r2], #0 @ read back dpll value
tst r0, #1 << 4 @ want lock mode?
beq out @ nope
tst r4, #1 << 0 @ dpll rate locked?
beq lock @ try again
out:
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
ENTRY(omap1_sram_reprogram_clock_sz)
.word . - omap1_sram_reprogram_clock