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Many user space API headers are missing licensing information, which makes it hard for compliance tools to determine the correct license. By default are files without license information under the default license of the kernel, which is GPLV2. Marking them GPLV2 would exclude them from being included in non GPLV2 code, which is obviously not intended. The user space API headers fall under the syscall exception which is in the kernels COPYING file: NOTE! This copyright does *not* cover user programs that use kernel services by normal system calls - this is merely considered normal use of the kernel, and does *not* fall under the heading of "derived work". otherwise syscall usage would not be possible. Update the files which contain no license information with an SPDX license identifier. The chosen identifier is 'GPL-2.0 WITH Linux-syscall-note' which is the officially assigned identifier for the Linux syscall exception. SPDX license identifiers are a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. See the previous patch in this series for the methodology of how this patch was researched. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
168 lines
5.6 KiB
C
168 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*----------------------------------------
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PERFORMANCE INSTRUMENTATION
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Guillaume Thouvenin 08/10/98
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David S. Miller 10/06/98
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---------------------------------------*/
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#ifndef PERF_COUNTER_API
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#define PERF_COUNTER_API
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/* sys_perfctr() interface. First arg is operation code
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* from enumeration below. The meaning of further arguments
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* are determined by the operation code.
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*
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* NOTE: This system call is no longer provided, use the perf_events
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* infrastructure.
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*
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* Pointers which are passed by the user are pointers to 64-bit
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* integers.
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*
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* Once enabled, performance counter state is retained until the
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* process either exits or performs an exec. That is, performance
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* counters remain enabled for fork/clone children.
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*/
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enum perfctr_opcode {
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/* Enable UltraSparc performance counters, ARG0 is pointer
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* to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
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* to 64-bit accumulator for D1 counter. ARG2 is a pointer to
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* the initial PCR register value to use.
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*/
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PERFCTR_ON,
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/* Disable UltraSparc performance counters. The PCR is written
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* with zero and the user counter accumulator pointers and
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* working PCR register value are forgotten.
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*/
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PERFCTR_OFF,
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/* Add current D0 and D1 PIC values into user pointers given
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* in PERFCTR_ON operation. The PIC is cleared before returning.
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*/
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PERFCTR_READ,
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/* Clear the PIC register. */
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PERFCTR_CLRPIC,
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/* Begin using a new PCR value, the pointer to which is passed
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* in ARG0. The PIC is also cleared after the new PCR value is
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* written.
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*/
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PERFCTR_SETPCR,
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/* Store in pointer given in ARG0 the current PCR register value
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* being used.
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*/
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PERFCTR_GETPCR
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};
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#define PRIV 0x00000001
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#define SYS 0x00000002
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#define USR 0x00000004
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/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
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#define CYCLE_CNT 0x00000000
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#define INSTR_CNT 0x00000010
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#define DISPATCH0_IC_MISS 0x00000020
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#define DISPATCH0_STOREBUF 0x00000030
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#define IC_REF 0x00000080
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#define DC_RD 0x00000090
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#define DC_WR 0x000000A0
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#define LOAD_USE 0x000000B0
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#define EC_REF 0x000000C0
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#define EC_WRITE_HIT_RDO 0x000000D0
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#define EC_SNOOP_INV 0x000000E0
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#define EC_RD_HIT 0x000000F0
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/* Pic.S0 Selection Bit Field Encoding, Ultra-III */
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#define US3_CYCLE_CNT 0x00000000
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#define US3_INSTR_CNT 0x00000010
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#define US3_DISPATCH0_IC_MISS 0x00000020
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#define US3_DISPATCH0_BR_TGT 0x00000030
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#define US3_DISPATCH0_2ND_BR 0x00000040
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#define US3_RSTALL_STOREQ 0x00000050
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#define US3_RSTALL_IU_USE 0x00000060
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#define US3_IC_REF 0x00000080
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#define US3_DC_RD 0x00000090
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#define US3_DC_WR 0x000000a0
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#define US3_EC_REF 0x000000c0
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#define US3_EC_WR_HIT_RTO 0x000000d0
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#define US3_EC_SNOOP_INV 0x000000e0
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#define US3_EC_RD_MISS 0x000000f0
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#define US3_PC_PORT0_RD 0x00000100
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#define US3_SI_SNOOP 0x00000110
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#define US3_SI_CIQ_FLOW 0x00000120
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#define US3_SI_OWNED 0x00000130
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#define US3_SW_COUNT_0 0x00000140
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#define US3_IU_BR_MISS_TAKEN 0x00000150
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#define US3_IU_BR_COUNT_TAKEN 0x00000160
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#define US3_DISP_RS_MISPRED 0x00000170
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#define US3_FA_PIPE_COMPL 0x00000180
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#define US3_MC_READS_0 0x00000200
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#define US3_MC_READS_1 0x00000210
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#define US3_MC_READS_2 0x00000220
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#define US3_MC_READS_3 0x00000230
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#define US3_MC_STALLS_0 0x00000240
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#define US3_MC_STALLS_2 0x00000250
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/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
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#define CYCLE_CNT_D1 0x00000000
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#define INSTR_CNT_D1 0x00000800
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#define DISPATCH0_IC_MISPRED 0x00001000
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#define DISPATCH0_FP_USE 0x00001800
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#define IC_HIT 0x00004000
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#define DC_RD_HIT 0x00004800
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#define DC_WR_HIT 0x00005000
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#define LOAD_USE_RAW 0x00005800
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#define EC_HIT 0x00006000
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#define EC_WB 0x00006800
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#define EC_SNOOP_CB 0x00007000
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#define EC_IT_HIT 0x00007800
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/* Pic.S1 Selection Bit Field Encoding, Ultra-III */
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#define US3_CYCLE_CNT_D1 0x00000000
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#define US3_INSTR_CNT_D1 0x00000800
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#define US3_DISPATCH0_MISPRED 0x00001000
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#define US3_IC_MISS_CANCELLED 0x00001800
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#define US3_RE_ENDIAN_MISS 0x00002000
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#define US3_RE_FPU_BYPASS 0x00002800
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#define US3_RE_DC_MISS 0x00003000
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#define US3_RE_EC_MISS 0x00003800
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#define US3_IC_MISS 0x00004000
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#define US3_DC_RD_MISS 0x00004800
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#define US3_DC_WR_MISS 0x00005000
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#define US3_RSTALL_FP_USE 0x00005800
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#define US3_EC_MISSES 0x00006000
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#define US3_EC_WB 0x00006800
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#define US3_EC_SNOOP_CB 0x00007000
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#define US3_EC_IC_MISS 0x00007800
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#define US3_RE_PC_MISS 0x00008000
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#define US3_ITLB_MISS 0x00008800
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#define US3_DTLB_MISS 0x00009000
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#define US3_WC_MISS 0x00009800
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#define US3_WC_SNOOP_CB 0x0000a000
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#define US3_WC_SCRUBBED 0x0000a800
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#define US3_WC_WB_WO_READ 0x0000b000
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#define US3_PC_SOFT_HIT 0x0000c000
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#define US3_PC_SNOOP_INV 0x0000c800
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#define US3_PC_HARD_HIT 0x0000d000
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#define US3_PC_PORT1_RD 0x0000d800
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#define US3_SW_COUNT_1 0x0000e000
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#define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
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#define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
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#define US3_PC_MS_MISSES 0x0000f800
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#define US3_MC_WRITES_0 0x00010800
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#define US3_MC_WRITES_1 0x00011000
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#define US3_MC_WRITES_2 0x00011800
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#define US3_MC_WRITES_3 0x00012000
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#define US3_MC_STALLS_1 0x00012800
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#define US3_MC_STALLS_3 0x00013000
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#define US3_RE_RAW_MISS 0x00013800
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#define US3_FM_PIPE_COMPLETION 0x00014000
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struct vcounter_struct {
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unsigned long long vcnt0;
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unsigned long long vcnt1;
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};
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#endif /* !(PERF_COUNTER_API) */
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