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https://github.com/torvalds/linux
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cd70d4659f
Currently a PAMU driver patch is very likely to receive some checkpatch complaints about the code in the context of the patch. This patch is an attempt to fix most of that and make the driver more readable Also fixed a subset of the sparse and coccinelle reported issues. Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
411 lines
13 KiB
C
411 lines
13 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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*/
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#ifndef __FSL_PAMU_H
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#define __FSL_PAMU_H
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#include <linux/iommu.h>
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#include <asm/fsl_pamu_stash.h>
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/* Bit Field macros
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* v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load
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*/
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#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << m##_SHIFT) & (m)))
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#define get_bf(v, m) (((v) & (m)) >> m##_SHIFT)
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/* PAMU CCSR space */
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#define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
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#define PAMU_PE 0x40000000 /* enable PAMU */
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/* PAMU_OFFSET to the next pamu space in ccsr */
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#define PAMU_OFFSET 0x1000
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#define PAMU_MMAP_REGS_BASE 0
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struct pamu_mmap_regs {
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u32 ppbah;
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u32 ppbal;
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u32 pplah;
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u32 pplal;
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u32 spbah;
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u32 spbal;
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u32 splah;
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u32 splal;
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u32 obah;
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u32 obal;
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u32 olah;
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u32 olal;
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};
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/* PAMU Error Registers */
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#define PAMU_POES1 0x0040
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#define PAMU_POES2 0x0044
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#define PAMU_POEAH 0x0048
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#define PAMU_POEAL 0x004C
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#define PAMU_AVS1 0x0050
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#define PAMU_AVS1_AV 0x1
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#define PAMU_AVS1_OTV 0x6
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#define PAMU_AVS1_APV 0x78
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#define PAMU_AVS1_WAV 0x380
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#define PAMU_AVS1_LAV 0x1c00
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#define PAMU_AVS1_GCV 0x2000
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#define PAMU_AVS1_PDV 0x4000
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#define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
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| PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
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#define PAMU_AVS1_LIODN_SHIFT 16
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#define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
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#define PAMU_AVS2 0x0054
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#define PAMU_AVAH 0x0058
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#define PAMU_AVAL 0x005C
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#define PAMU_EECTL 0x0060
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#define PAMU_EEDIS 0x0064
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#define PAMU_EEINTEN 0x0068
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#define PAMU_EEDET 0x006C
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#define PAMU_EEATTR 0x0070
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#define PAMU_EEAHI 0x0074
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#define PAMU_EEALO 0x0078
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#define PAMU_EEDHI 0X007C
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#define PAMU_EEDLO 0x0080
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#define PAMU_EECC 0x0084
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#define PAMU_UDAD 0x0090
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/* PAMU Revision Registers */
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#define PAMU_PR1 0x0BF8
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#define PAMU_PR2 0x0BFC
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/* PAMU version mask */
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#define PAMU_PR1_MASK 0xffff
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/* PAMU Capabilities Registers */
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#define PAMU_PC1 0x0C00
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#define PAMU_PC2 0x0C04
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#define PAMU_PC3 0x0C08
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#define PAMU_PC4 0x0C0C
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/* PAMU Control Register */
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#define PAMU_PC 0x0C10
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/* PAMU control defs */
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#define PAMU_CONTROL 0x0C10
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#define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */
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#define PAMU_PC_PE 0x40000000 /* PAMU enable bit */
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#define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
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#define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
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#define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
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#define PAMU_PFA1 0x0C14
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#define PAMU_PFA2 0x0C18
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#define PAMU_PC2_MLIODN(X) ((X) >> 16)
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#define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
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/* PAMU Interrupt control and Status Register */
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#define PAMU_PICS 0x0C1C
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#define PAMU_ACCESS_VIOLATION_STAT 0x8
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#define PAMU_ACCESS_VIOLATION_ENABLE 0x4
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/* PAMU Debug Registers */
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#define PAMU_PD1 0x0F00
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#define PAMU_PD2 0x0F04
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#define PAMU_PD3 0x0F08
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#define PAMU_PD4 0x0F0C
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#define PAACE_AP_PERMS_DENIED 0x0
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#define PAACE_AP_PERMS_QUERY 0x1
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#define PAACE_AP_PERMS_UPDATE 0x2
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#define PAACE_AP_PERMS_ALL 0x3
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#define PAACE_DD_TO_HOST 0x0
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#define PAACE_DD_TO_IO 0x1
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#define PAACE_PT_PRIMARY 0x0
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#define PAACE_PT_SECONDARY 0x1
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#define PAACE_V_INVALID 0x0
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#define PAACE_V_VALID 0x1
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#define PAACE_MW_SUBWINDOWS 0x1
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#define PAACE_WSE_4K 0xB
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#define PAACE_WSE_8K 0xC
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#define PAACE_WSE_16K 0xD
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#define PAACE_WSE_32K 0xE
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#define PAACE_WSE_64K 0xF
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#define PAACE_WSE_128K 0x10
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#define PAACE_WSE_256K 0x11
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#define PAACE_WSE_512K 0x12
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#define PAACE_WSE_1M 0x13
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#define PAACE_WSE_2M 0x14
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#define PAACE_WSE_4M 0x15
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#define PAACE_WSE_8M 0x16
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#define PAACE_WSE_16M 0x17
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#define PAACE_WSE_32M 0x18
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#define PAACE_WSE_64M 0x19
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#define PAACE_WSE_128M 0x1A
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#define PAACE_WSE_256M 0x1B
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#define PAACE_WSE_512M 0x1C
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#define PAACE_WSE_1G 0x1D
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#define PAACE_WSE_2G 0x1E
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#define PAACE_WSE_4G 0x1F
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#define PAACE_DID_PCI_EXPRESS_1 0x00
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#define PAACE_DID_PCI_EXPRESS_2 0x01
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#define PAACE_DID_PCI_EXPRESS_3 0x02
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#define PAACE_DID_PCI_EXPRESS_4 0x03
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#define PAACE_DID_LOCAL_BUS 0x04
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#define PAACE_DID_SRIO 0x0C
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#define PAACE_DID_MEM_1 0x10
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#define PAACE_DID_MEM_2 0x11
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#define PAACE_DID_MEM_3 0x12
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#define PAACE_DID_MEM_4 0x13
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#define PAACE_DID_MEM_1_2 0x14
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#define PAACE_DID_MEM_3_4 0x15
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#define PAACE_DID_MEM_1_4 0x16
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#define PAACE_DID_BM_SW_PORTAL 0x18
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#define PAACE_DID_PAMU 0x1C
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#define PAACE_DID_CAAM 0x21
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#define PAACE_DID_QM_SW_PORTAL 0x3C
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#define PAACE_DID_CORE0_INST 0x80
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#define PAACE_DID_CORE0_DATA 0x81
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#define PAACE_DID_CORE1_INST 0x82
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#define PAACE_DID_CORE1_DATA 0x83
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#define PAACE_DID_CORE2_INST 0x84
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#define PAACE_DID_CORE2_DATA 0x85
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#define PAACE_DID_CORE3_INST 0x86
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#define PAACE_DID_CORE3_DATA 0x87
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#define PAACE_DID_CORE4_INST 0x88
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#define PAACE_DID_CORE4_DATA 0x89
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#define PAACE_DID_CORE5_INST 0x8A
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#define PAACE_DID_CORE5_DATA 0x8B
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#define PAACE_DID_CORE6_INST 0x8C
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#define PAACE_DID_CORE6_DATA 0x8D
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#define PAACE_DID_CORE7_INST 0x8E
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#define PAACE_DID_CORE7_DATA 0x8F
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#define PAACE_DID_BROADCAST 0xFF
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#define PAACE_ATM_NO_XLATE 0x00
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#define PAACE_ATM_WINDOW_XLATE 0x01
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#define PAACE_ATM_PAGE_XLATE 0x02
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#define PAACE_ATM_WIN_PG_XLATE (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
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#define PAACE_OTM_NO_XLATE 0x00
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#define PAACE_OTM_IMMEDIATE 0x01
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#define PAACE_OTM_INDEXED 0x02
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#define PAACE_OTM_RESERVED 0x03
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#define PAACE_M_COHERENCE_REQ 0x01
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#define PAACE_PID_0 0x0
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#define PAACE_PID_1 0x1
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#define PAACE_PID_2 0x2
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#define PAACE_PID_3 0x3
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#define PAACE_PID_4 0x4
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#define PAACE_PID_5 0x5
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#define PAACE_PID_6 0x6
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#define PAACE_PID_7 0x7
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#define PAACE_TCEF_FORMAT0_8B 0x00
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#define PAACE_TCEF_FORMAT1_RSVD 0x01
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/*
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* Hard coded value for the PAACT size to accommodate
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* maximum LIODN value generated by u-boot.
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*/
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#define PAACE_NUMBER_ENTRIES 0x500
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/* Hard coded value for the SPAACT size */
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#define SPAACE_NUMBER_ENTRIES 0x800
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#define OME_NUMBER_ENTRIES 16
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/* PAACE Bit Field Defines */
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#define PPAACE_AF_WBAL 0xfffff000
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#define PPAACE_AF_WBAL_SHIFT 12
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#define PPAACE_AF_WSE 0x00000fc0
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#define PPAACE_AF_WSE_SHIFT 6
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#define PPAACE_AF_MW 0x00000020
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#define PPAACE_AF_MW_SHIFT 5
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#define SPAACE_AF_LIODN 0xffff0000
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#define SPAACE_AF_LIODN_SHIFT 16
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#define PAACE_AF_AP 0x00000018
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#define PAACE_AF_AP_SHIFT 3
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#define PAACE_AF_DD 0x00000004
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#define PAACE_AF_DD_SHIFT 2
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#define PAACE_AF_PT 0x00000002
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#define PAACE_AF_PT_SHIFT 1
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#define PAACE_AF_V 0x00000001
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#define PAACE_AF_V_SHIFT 0
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#define PAACE_DA_HOST_CR 0x80
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#define PAACE_DA_HOST_CR_SHIFT 7
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#define PAACE_IA_CID 0x00FF0000
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#define PAACE_IA_CID_SHIFT 16
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#define PAACE_IA_WCE 0x000000F0
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#define PAACE_IA_WCE_SHIFT 4
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#define PAACE_IA_ATM 0x0000000C
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#define PAACE_IA_ATM_SHIFT 2
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#define PAACE_IA_OTM 0x00000003
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#define PAACE_IA_OTM_SHIFT 0
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#define PAACE_WIN_TWBAL 0xfffff000
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#define PAACE_WIN_TWBAL_SHIFT 12
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#define PAACE_WIN_SWSE 0x00000fc0
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#define PAACE_WIN_SWSE_SHIFT 6
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/* PAMU Data Structures */
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/* primary / secondary paact structure */
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struct paace {
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/* PAACE Offset 0x00 */
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u32 wbah; /* only valid for Primary PAACE */
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u32 addr_bitfields; /* See P/S PAACE_AF_* */
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/* PAACE Offset 0x08 */
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/* Interpretation of first 32 bits dependent on DD above */
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union {
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struct {
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/* Destination ID, see PAACE_DID_* defines */
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u8 did;
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/* Partition ID */
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u8 pid;
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/* Snoop ID */
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u8 snpid;
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/* coherency_required : 1 reserved : 7 */
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u8 coherency_required; /* See PAACE_DA_* */
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} to_host;
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struct {
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/* Destination ID, see PAACE_DID_* defines */
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u8 did;
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u8 reserved1;
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u16 reserved2;
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} to_io;
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} domain_attr;
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/* Implementation attributes + window count + address & operation translation modes */
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u32 impl_attr; /* See PAACE_IA_* */
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/* PAACE Offset 0x10 */
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/* Translated window base address */
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u32 twbah;
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u32 win_bitfields; /* See PAACE_WIN_* */
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/* PAACE Offset 0x18 */
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/* first secondary paace entry */
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u32 fspi; /* only valid for Primary PAACE */
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union {
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struct {
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u8 ioea;
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u8 moea;
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u8 ioeb;
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u8 moeb;
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} immed_ot;
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struct {
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u16 reserved;
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u16 omi;
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} index_ot;
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} op_encode;
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/* PAACE Offsets 0x20-0x38 */
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u32 reserved[8]; /* not currently implemented */
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};
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/* OME : Operation mapping entry
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* MOE : Mapped Operation Encodings
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* The operation mapping table is table containing operation mapping entries (OME).
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* The index of a particular OME is programmed in the PAACE entry for translation
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* in bound I/O operations corresponding to an LIODN. The OMT is used for translation
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* specifically in case of the indexed translation mode. Each OME contains a 128
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* byte mapped operation encoding (MOE), where each byte represents an MOE.
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*/
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#define NUM_MOE 128
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struct ome {
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u8 moe[NUM_MOE];
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} __packed;
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#define PAACT_SIZE (sizeof(struct paace) * PAACE_NUMBER_ENTRIES)
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#define SPAACT_SIZE (sizeof(struct paace) * SPAACE_NUMBER_ENTRIES)
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#define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES)
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#define PAMU_PAGE_SHIFT 12
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#define PAMU_PAGE_SIZE 4096ULL
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#define IOE_READ 0x00
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#define IOE_READ_IDX 0x00
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#define IOE_WRITE 0x81
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#define IOE_WRITE_IDX 0x01
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#define IOE_EREAD0 0x82 /* Enhanced read type 0 */
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#define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
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#define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
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#define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
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#define IOE_DIRECT0 0x84 /* Directive type 0 */
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#define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
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#define IOE_EREAD1 0x85 /* Enhanced read type 1 */
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#define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
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#define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
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#define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
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#define IOE_DIRECT1 0x87 /* Directive type 1 */
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#define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
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#define IOE_RAC 0x8c /* Read with Atomic clear */
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#define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
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#define IOE_RAS 0x8d /* Read with Atomic set */
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#define IOE_RAS_IDX 0x0d /* Read with Atomic set */
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#define IOE_RAD 0x8e /* Read with Atomic decrement */
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#define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
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#define IOE_RAI 0x8f /* Read with Atomic increment */
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#define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
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#define EOE_READ 0x00
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#define EOE_WRITE 0x01
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#define EOE_RAC 0x0c /* Read with Atomic clear */
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#define EOE_RAS 0x0d /* Read with Atomic set */
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#define EOE_RAD 0x0e /* Read with Atomic decrement */
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#define EOE_RAI 0x0f /* Read with Atomic increment */
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#define EOE_LDEC 0x10 /* Load external cache */
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#define EOE_LDECL 0x11 /* Load external cache with stash lock */
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#define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
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#define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
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#define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
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#define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
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#define EOE_RSA 0x16 /* Read with stash allocate */
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#define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
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#define EOE_READI 0x18 /* Read with invalidate */
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#define EOE_RWNITC 0x19 /* Read with no intention to cache */
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#define EOE_WCI 0x1a /* Write cache inhibited */
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#define EOE_WWSA 0x1b /* Write with stash allocate */
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#define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
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#define EOE_WWSAO 0x1d /* Write with stash allocate only */
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#define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
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#define EOE_VALID 0x80
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/* Function prototypes */
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int pamu_domain_init(void);
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int pamu_enable_liodn(int liodn);
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int pamu_disable_liodn(int liodn);
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void pamu_free_subwins(int liodn);
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int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
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u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid,
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u32 subwin_cnt, int prot);
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int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
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phys_addr_t subwin_size, u32 omi, unsigned long rpn,
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uint32_t snoopid, u32 stashid, int enable, int prot);
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u32 get_stash_id(u32 stash_dest_hint, u32 vcpu);
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void get_ome_index(u32 *omi_index, struct device *dev);
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int pamu_update_paace_stash(int liodn, u32 subwin, u32 value);
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int pamu_disable_spaace(int liodn, u32 subwin);
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u32 pamu_get_max_subwin_cnt(void);
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#endif /* __FSL_PAMU_H */
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