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Both PHYs are sharing one reset line. With recent improvements to the reset framework we can now also use reset_control_reset with shared resets. This allows us to drop some workarounds where the reset was only specified for one PHY but not the other, to make sure that the reset it only executed once (as the reset framework was not able to use reset_control_reset with shared reset lines). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
286 lines
8.6 KiB
C
286 lines
8.6 KiB
C
/*
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* Meson8b and GXBB USB2 PHY driver
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*
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* Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/usb/of.h>
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#define REG_CONFIG 0x00
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#define REG_CONFIG_CLK_EN BIT(0)
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#define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
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#define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
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#define REG_CONFIG_CLK_32k_ALTSEL BIT(15)
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#define REG_CONFIG_TEST_TRIG BIT(31)
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#define REG_CTRL 0x04
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#define REG_CTRL_SOFT_PRST BIT(0)
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#define REG_CTRL_SOFT_HRESET BIT(1)
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#define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
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#define REG_CTRL_CLK_DET_RST BIT(4)
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#define REG_CTRL_INTR_SEL BIT(5)
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#define REG_CTRL_CLK_DETECTED BIT(8)
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#define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9)
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#define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
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#define REG_CTRL_POWER_ON_RESET BIT(15)
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#define REG_CTRL_SLEEPM BIT(16)
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#define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17)
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#define REG_CTRL_TX_BITSTUFF_ENN BIT(18)
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#define REG_CTRL_COMMON_ON BIT(19)
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#define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)
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#define REG_CTRL_REF_CLK_SEL_SHIFT 20
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#define REG_CTRL_FSEL_MASK GENMASK(24, 22)
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#define REG_CTRL_FSEL_SHIFT 22
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#define REG_CTRL_PORT_RESET BIT(25)
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#define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
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#define REG_ENDP_INTR 0x08
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/* bits [31:26], [24:21] and [15:3] seem to be read-only */
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#define REG_ADP_BC 0x0c
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#define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
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#define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
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#define REG_ADP_BC_OTG_DISABLE BIT(2)
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#define REG_ADP_BC_ID_PULLUP BIT(3)
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#define REG_ADP_BC_DRV_VBUS BIT(4)
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#define REG_ADP_BC_ADP_PRB_EN BIT(5)
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#define REG_ADP_BC_ADP_DISCHARGE BIT(6)
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#define REG_ADP_BC_ADP_CHARGE BIT(7)
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#define REG_ADP_BC_SESS_END BIT(8)
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#define REG_ADP_BC_DEVICE_SESS_VLD BIT(9)
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#define REG_ADP_BC_B_VALID BIT(10)
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#define REG_ADP_BC_A_VALID BIT(11)
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#define REG_ADP_BC_ID_DIG BIT(12)
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#define REG_ADP_BC_VBUS_VALID BIT(13)
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#define REG_ADP_BC_ADP_PROBE BIT(14)
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#define REG_ADP_BC_ADP_SENSE BIT(15)
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#define REG_ADP_BC_ACA_ENABLE BIT(16)
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#define REG_ADP_BC_DCD_ENABLE BIT(17)
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#define REG_ADP_BC_VDAT_DET_EN_B BIT(18)
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#define REG_ADP_BC_VDAT_SRC_EN_B BIT(19)
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#define REG_ADP_BC_CHARGE_SEL BIT(20)
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#define REG_ADP_BC_CHARGE_DETECT BIT(21)
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#define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22)
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#define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23)
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#define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24)
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#define REG_ADP_BC_ACA_PIN_GND BIT(25)
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#define REG_ADP_BC_ACA_PIN_FLOAT BIT(26)
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#define REG_DBG_UART 0x14
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#define REG_TEST 0x18
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#define REG_TEST_DATA_IN_MASK GENMASK(3, 0)
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#define REG_TEST_EN_MASK GENMASK(7, 4)
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#define REG_TEST_ADDR_MASK GENMASK(11, 8)
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#define REG_TEST_DATA_OUT_SEL BIT(12)
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#define REG_TEST_CLK BIT(13)
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#define REG_TEST_VA_TEST_EN_B_MASK GENMASK(15, 14)
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#define REG_TEST_DATA_OUT_MASK GENMASK(19, 16)
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#define REG_TEST_DISABLE_ID_PULLUP BIT(20)
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#define REG_TUNE 0x1c
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#define REG_TUNE_TX_RES_TUNE_MASK GENMASK(1, 0)
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#define REG_TUNE_TX_HSXV_TUNE_MASK GENMASK(3, 2)
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#define REG_TUNE_TX_VREF_TUNE_MASK GENMASK(7, 4)
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#define REG_TUNE_TX_RISE_TUNE_MASK GENMASK(9, 8)
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#define REG_TUNE_TX_PREEMP_PULSE_TUNE BIT(10)
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#define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK GENMASK(12, 11)
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#define REG_TUNE_TX_FSLS_TUNE_MASK GENMASK(16, 13)
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#define REG_TUNE_SQRX_TUNE_MASK GENMASK(19, 17)
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#define REG_TUNE_OTG_TUNE GENMASK(22, 20)
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#define REG_TUNE_COMP_DIS_TUNE GENMASK(25, 23)
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#define REG_TUNE_HOST_DM_PULLDOWN BIT(26)
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#define REG_TUNE_HOST_DP_PULLDOWN BIT(27)
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#define RESET_COMPLETE_TIME 500
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#define ACA_ENABLE_COMPLETE_TIME 50
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struct phy_meson8b_usb2_priv {
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void __iomem *regs;
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enum usb_dr_mode dr_mode;
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struct clk *clk_usb_general;
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struct clk *clk_usb;
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struct reset_control *reset;
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};
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static u32 phy_meson8b_usb2_read(struct phy_meson8b_usb2_priv *phy_priv,
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u32 reg)
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{
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return readl(phy_priv->regs + reg);
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}
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static void phy_meson8b_usb2_mask_bits(struct phy_meson8b_usb2_priv *phy_priv,
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u32 reg, u32 mask, u32 value)
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{
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u32 data;
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data = phy_meson8b_usb2_read(phy_priv, reg);
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data &= ~mask;
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data |= (value & mask);
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writel(data, phy_priv->regs + reg);
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}
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static int phy_meson8b_usb2_power_on(struct phy *phy)
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{
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struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
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int ret;
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if (!IS_ERR_OR_NULL(priv->reset)) {
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ret = reset_control_reset(priv->reset);
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if (ret) {
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dev_err(&phy->dev, "Failed to trigger USB reset\n");
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return ret;
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}
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}
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ret = clk_prepare_enable(priv->clk_usb_general);
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if (ret) {
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dev_err(&phy->dev, "Failed to enable USB general clock\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->clk_usb);
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if (ret) {
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dev_err(&phy->dev, "Failed to enable USB DDR clock\n");
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clk_disable_unprepare(priv->clk_usb_general);
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return ret;
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}
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phy_meson8b_usb2_mask_bits(priv, REG_CONFIG, REG_CONFIG_CLK_32k_ALTSEL,
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REG_CONFIG_CLK_32k_ALTSEL);
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phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_REF_CLK_SEL_MASK,
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0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
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phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_FSEL_MASK,
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0x5 << REG_CTRL_FSEL_SHIFT);
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/* reset the PHY */
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phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET,
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REG_CTRL_POWER_ON_RESET);
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udelay(RESET_COMPLETE_TIME);
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phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET, 0);
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udelay(RESET_COMPLETE_TIME);
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phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT,
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REG_CTRL_SOF_TOGGLE_OUT);
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if (priv->dr_mode == USB_DR_MODE_HOST) {
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phy_meson8b_usb2_mask_bits(priv, REG_ADP_BC,
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REG_ADP_BC_ACA_ENABLE,
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REG_ADP_BC_ACA_ENABLE);
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udelay(ACA_ENABLE_COMPLETE_TIME);
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if (phy_meson8b_usb2_read(priv, REG_ADP_BC) &
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REG_ADP_BC_ACA_PIN_FLOAT) {
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dev_warn(&phy->dev, "USB ID detect failed!\n");
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clk_disable_unprepare(priv->clk_usb);
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clk_disable_unprepare(priv->clk_usb_general);
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return -EINVAL;
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}
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}
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return 0;
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}
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static int phy_meson8b_usb2_power_off(struct phy *phy)
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{
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struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
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clk_disable_unprepare(priv->clk_usb);
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clk_disable_unprepare(priv->clk_usb_general);
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return 0;
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}
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static const struct phy_ops phy_meson8b_usb2_ops = {
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.power_on = phy_meson8b_usb2_power_on,
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.power_off = phy_meson8b_usb2_power_off,
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.owner = THIS_MODULE,
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};
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static int phy_meson8b_usb2_probe(struct platform_device *pdev)
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{
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struct phy_meson8b_usb2_priv *priv;
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struct resource *res;
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struct phy *phy;
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struct phy_provider *phy_provider;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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priv->clk_usb_general = devm_clk_get(&pdev->dev, "usb_general");
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if (IS_ERR(priv->clk_usb_general))
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return PTR_ERR(priv->clk_usb_general);
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priv->clk_usb = devm_clk_get(&pdev->dev, "usb");
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if (IS_ERR(priv->clk_usb))
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return PTR_ERR(priv->clk_usb);
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priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
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if (PTR_ERR(priv->reset) == -EPROBE_DEFER)
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return PTR_ERR(priv->reset);
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priv->dr_mode = of_usb_get_dr_mode_by_phy(pdev->dev.of_node, -1);
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if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
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dev_err(&pdev->dev,
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"missing dual role configuration of the controller\n");
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return -EINVAL;
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}
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phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops);
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if (IS_ERR(phy)) {
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dev_err(&pdev->dev, "failed to create PHY\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, priv);
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phy_provider =
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devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id phy_meson8b_usb2_of_match[] = {
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{ .compatible = "amlogic,meson8b-usb2-phy", },
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{ .compatible = "amlogic,meson-gxbb-usb2-phy", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, phy_meson8b_usb2_of_match);
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static struct platform_driver phy_meson8b_usb2_driver = {
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.probe = phy_meson8b_usb2_probe,
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.driver = {
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.name = "phy-meson-usb2",
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.of_match_table = phy_meson8b_usb2_of_match,
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},
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};
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module_platform_driver(phy_meson8b_usb2_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Meson8b and GXBB USB2 PHY driver");
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MODULE_LICENSE("GPL");
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